A Multi-threaded Fast Hardware Compiler for HDLs
Authors: 
Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose RenauAuthors Info & Claims
Pages 25 - 36
Abstract
A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in compilation technology is limited.
We design and implement LiveHD, a new multi-threaded, fast, and generic compilation framework across many HDLs (FIRRTL, Verilog, and Pyrope). We propose new parallel full and bottom-up passes to handle HDLs. The resulting compiler can parallelize all the compiler steps.
LiveHD can achieve 5.5x scalability speedup when elaborating a CHISEL RISC-V Manycore. It also gets from 7.7x to 8.4x scalability speedup for a benchmark designed in all three HDLs. This is achieved with a fast single-threaded LiveHD baseline with 6x speedup compared to compilers such as Scala-FIRRTL and 8.6x against Yosys on Verilog.
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Index Terms
- A Multi-threaded Fast Hardware Compiler for HDLs
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Published In
February 2023
249 pages
ISBN:9798400700880
DOI:10.1145/3578360
- General Chair:
- Clark Verbrugge,
- Program Chairs:
- Ondřej Lhoták,
- Xipeng Shen
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Published: 17 February 2023
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