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Multi-node static logic implications for redundancy identification

Published: 01 January 2000 Publication History
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References

[1]
S. T. Chakradhar and V. D. Agrawal. A Transitive Closure Based Algorithm for Test Generation. In Proc. of the Design Automation Conf. ACM/IEEE, June 1991.
[2]
S. T. Chakradhar and V. D. Agrawal. A Transitive Closure Algorithm for Test Generation. In Trans. Computer-Aided Design. IEEE, June 1993.
[3]
M. A. Iyer and M. Abramovici. Low Cost Redundancy Identification for Combinational Circuits. Proc. Int. Conference VLSI Design, June 1994.
[4]
M. A. Iyer and M. Abramovici. FIRE: A Fault independent Combinational Redundancy Identification Algorithm. Trans. VLSI systems, June 1996.
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W. Kunz and D. K. Pradhan. Recursive learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits. Trans. on CAD, May 1993.
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J. Rajski and H. Cox. A Method to Calculate Necessary Assignments in ATPG. In Proc. of the Int'l. Test Conf. IEEE, September 1990.
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Zhao, M. Rudnick, and Janak Patel. Static Logic Implication with Application to Fast Redundancy Identification. VLSI Test Syrnposi~trn, April 1997.

Cited By

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  • (2010)A cost effective approach for online error detection using invariant relationshipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204359029:5(788-801)Online publication date: 1-May-2010
  • (2009)Detecting errors using multi-cycle invariance informationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874815(791-796)Online publication date: 20-Apr-2009
  • (2009)Detecting errors using multi-cycle invariance information2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090771(791-796)Online publication date: Apr-2009
  • Show More Cited By

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        cover image ACM Conferences
        DATE '00: Proceedings of the conference on Design, automation and test in Europe
        January 2000
        707 pages
        ISBN:1581132441
        DOI:10.1145/343647
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        • EDAA: European Design Automation Association
        • ECSI
        • EDAC: Electronic Design Automation Consortium
        • SIGDA: ACM Special Interest Group on Design Automation
        • IEEE-CS: Computer Society
        • IFIP: International Federation for Information Processing
        • The Russian Academy of Sciences: The Russian Academy of Sciences

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        Publication History

        Published: 01 January 2000

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        Sponsor:
        • EDAA
        • EDAC
        • SIGDA
        • IEEE-CS
        • IFIP
        • The Russian Academy of Sciences
        DATE00: Design Automation and Test in Europe
        March 27 - 30, 2000
        Paris, France

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        Overall Acceptance Rate 518 of 1,794 submissions, 29%

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        Cited By

        View all
        • (2010)A cost effective approach for online error detection using invariant relationshipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204359029:5(788-801)Online publication date: 1-May-2010
        • (2009)Detecting errors using multi-cycle invariance informationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874815(791-796)Online publication date: 20-Apr-2009
        • (2009)Detecting errors using multi-cycle invariance information2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090771(791-796)Online publication date: Apr-2009
        • (2006)Mining global constraints for improving bounded sequential equivalence checkingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147098(743-748)Online publication date: 24-Jul-2006
        • (2006)Mining global constraints for improving bounded sequential equivalence checking2006 43rd ACM/IEEE Design Automation Conference10.1109/DAC.2006.229319(743-748)Online publication date: 2006
        • (2005)Untestable fault identification through enhanced necessary value assignmentsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057705(176-181)Online publication date: 17-Apr-2005

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