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Barriers reconsidered, friendlier still!

Published: 15 June 2012 Publication History

Abstract

Read and write barriers mediate access to the heap allowing the collector to control and monitor mutator actions. For this reason, barriers are a powerful tool in the design of any heap management algorithm, but the prevailing wisdom is that they impose significant costs. However, changes in hardware and workloads make these costs a moving target. Here, we measure the cost of a range of useful barriers on a range of modern hardware and workloads. We confirm some old results and overturn others. We evaluate the microarchitectural sensitivity of barrier performance and the differences among benchmark suites. We also consider barriers in context, focusing on their behavior when used in combination, and investigate a known pathology and evaluate solutions. Our results show that read and write barriers have average overheads as low as 5.4% and 0.9% respectively. We find that barrier overheads are more exposed on the workload provided by the modern DaCapo benchmarks than on old SPECjvm98 benchmarks. Moreover, there are differences in barrier behavior between in-order and out-of- order machines, and their respective memory subsystems, which indicate different barrier choices for different platforms. These changing costs mean that algorithm designers need to reconsider their design choices and the nature of their resulting algorithms in order to exploit the opportunities presented by modern hardware.

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Published In

cover image ACM Conferences
ISMM '12: Proceedings of the 2012 international symposium on Memory Management
June 2012
152 pages
ISBN:9781450313506
DOI:10.1145/2258996
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 47, Issue 11
    ISMM '12
    November 2012
    136 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/2426642
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 15 June 2012

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Author Tags

  1. garbage collection
  2. java
  3. memory management
  4. write barriers

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Cited By

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  • (2024)Mutator-Driven Object Placement using Load BarriersProceedings of the 21st ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes10.1145/3679007.3685060(14-27)Online publication date: 13-Sep-2024
  • (2023)Improving Garbage Collection Observability with Performance TracingProceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes10.1145/3617651.3622986(85-99)Online publication date: 19-Oct-2023
  • (2022)Low-latency, high-throughput garbage collectionProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523440(76-91)Online publication date: 9-Jun-2022
  • (2022)Distilling the Real Cost of Production Garbage Collectors2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS55109.2022.00005(46-57)Online publication date: May-2022
  • (2021)Supporting Legacy Libraries on Non-Volatile Memory: A User-Transparent Approach2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA52012.2021.00042(443-455)Online publication date: Jun-2021
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  • (2019)Design and analysis of field-logging write barriersProceedings of the 2019 ACM SIGPLAN International Symposium on Memory Management10.1145/3315573.3329981(103-114)Online publication date: 23-Jun-2019
  • (2019)Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2019.00017(93-105)Online publication date: Mar-2019
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