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Destage algorithms for disk arrays with non-volatile caches

Published: 01 May 1995 Publication History

Abstract

In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. In this paper, we study a number of algorithms for scheduling destages in a RAID-5 system. We introduce a new scheduling algorithm, called linear threshold scheduling, that adaptively varies the rate of destages to disks based on the instantaneous occupancy of the write cache. The performance of the algorithm is compared with that of a number of alternative scheduling approaches such as least-cost scheduling and high/low mark. The algorithms are evaluated in terms of their effectiveness in making destages transparent to the servicing of read requests from the host, disk utilization, and their ability to tolerate bursts in the workload without causing an overflow of the write cache. Our results show that linear threshold scheduling provides the best read performance of all the algorithms compared, while still maintaining a high degree of burst tolerance. An approximate implementation of the linear-threshold scheduling algorithm is also described. The approximate algorithm can be implemented with much lower overhead, yet its performance is virtually identical to that of the ideal algorithm.

References

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  • (2017)Impact of spintronic memory on multicore cache hierarchy designIET Computers & Digital Techniques10.1049/iet-cdt.2015.019011:2(51-59)Online publication date: 1-Mar-2017
  • (2016)Combined data caching and delayed parity update in RAID with SSD cacheProceedings of the 31st Annual ACM Symposium on Applied Computing10.1145/2851613.2851904(1771-1773)Online publication date: 4-Apr-2016
  • (2014)Improving Energy and Performance with Spintronics Caches in Multicore SystemsEuro-Par 2014: Parallel Processing Workshops10.1007/978-3-319-14313-2_24(279-290)Online publication date: 2014
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Published In

cover image ACM Conferences
ISCA '95: Proceedings of the 22nd annual international symposium on Computer architecture
July 1995
426 pages
ISBN:0897916980
DOI:10.1145/223982
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 23, Issue 2
    Special Issue: Proceedings of the 22nd annual international symposium on Computer architecture (ISCA '95)
    May 1995
    412 pages
    ISSN:0163-5964
    DOI:10.1145/225830
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1995

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ISCA95: International Conference on Computer Architecture
June 22 - 24, 1995
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Cited By

View all
  • (2017)Impact of spintronic memory on multicore cache hierarchy designIET Computers & Digital Techniques10.1049/iet-cdt.2015.019011:2(51-59)Online publication date: 1-Mar-2017
  • (2016)Combined data caching and delayed parity update in RAID with SSD cacheProceedings of the 31st Annual ACM Symposium on Applied Computing10.1145/2851613.2851904(1771-1773)Online publication date: 4-Apr-2016
  • (2014)Improving Energy and Performance with Spintronics Caches in Multicore SystemsEuro-Par 2014: Parallel Processing Workshops10.1007/978-3-319-14313-2_24(279-290)Online publication date: 2014
  • (2009)Improving application launch times with hybrid disksProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629486(373-382)Online publication date: 11-Oct-2009
  • (2005)The improved RAID 5 with the disk cache using the load-balanced destage algorithmHigh-Performance Computing and Networking10.1007/BFb0037246(966-968)Online publication date: 22-Jun-2005
  • (2004)STICSJournal of Parallel and Distributed Computing10.1016/j.jpdc.2004.05.00564:9(1069-1085)Online publication date: 1-Sep-2004
  • (2002)My Cache or Yours? Making Storage More ExclusiveProceedings of the General Track of the annual conference on USENIX Annual Technical Conference10.5555/647057.713858(161-175)Online publication date: 10-Jun-2002
  • (2002)RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/71.99320813:3(290-307)Online publication date: 1-Mar-2002
  • (1998)A New Hierarchical Disk ArchitectureIEEE Micro10.1109/40.74368618:6(64-76)Online publication date: 1-Nov-1998
  • (1998)Destage Algorithms for Disk Arrays with Nonvolatile CachesIEEE Transactions on Computers10.1109/12.66377047:2(228-235)Online publication date: 1-Feb-1998
  • Show More Cited By

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