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Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks

Published: 26 January 2012 Publication History

Abstract

We propose a flexibly-partitioned cache design that either drastically weakens or completely eliminates cache-based side channel attacks. The proposed Non-Monopolizable (NoMo) cache dynamically reserves cache lines for active threads and prevents other co-executing threads from evicting reserved lines. Unreserved lines remain available for dynamic sharing among threads. NoMo requires only simple modifications to the cache replacement logic, making it straightforward to adopt. It requires no software support enabling it to automatically protect pre-existing binaries. NoMo results in performance degradation of about 1% on average. We demonstrate that NoMo can provide strong security guarantees for the AES and Blowfish encryption algorithms.

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    cover image ACM Transactions on Architecture and Code Optimization
    ACM Transactions on Architecture and Code Optimization  Volume 8, Issue 4
    Special Issue on High-Performance Embedded Architectures and Compilers
    January 2012
    765 pages
    ISSN:1544-3566
    EISSN:1544-3973
    DOI:10.1145/2086696
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 26 January 2012
    Accepted: 01 November 2011
    Revised: 01 October 2011
    Received: 01 July 2011
    Published in TACO Volume 8, Issue 4

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    Author Tags

    1. Side-channel attacks
    2. secure architectures
    3. shared caches

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