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Spectral-based multi-way FPGA partitioning

Authors:

Pak K. Chan,

Martine D. F. Schlag,

Jason Y. ZienAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Pages 133 - 139

https://doi.org/10.1145/201310.201331

Published: 15 February 1995 Publication History

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Abstract

Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned subcircuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary goal is to produce routable subcircuits while maximizing FPGA device utilization. To assist the partitioner in assessing the routability of the partitioned subcircuits, we have developed a theory to predict the routability of the partitioned subcircuits prior to partitioning. Advancement over the current work is evidenced by results of experiments on the standard MCNC benchmarks.

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Cited By

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Cakir BMalik S(2019)Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit EmbeddingsACM Transactions on Design Automation of Electronic Systems10.1145/332908124:5(1-19)Online publication date: 12-Jun-2019
https://dl.acm.org/doi/10.1145/3329081
Cakir BMalik S(2018)Reverse Engineering Digital ICs through Geometric Embedding of Circuit GraphsACM Transactions on Design Automation of Electronic Systems10.1145/319312123:4(1-19)Online publication date: 18-Jul-2018
https://dl.acm.org/doi/10.1145/3193121
Mukherjee RLiu SMemik SMondal S(2008)A high-level clustering algorithm targeting dual Vdd FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139196513:4(1-20)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391965
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Index Terms

Spectral-based multi-way FPGA partitioning
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Information & Contributors

Information

Published In

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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Conference

FPGA95

Sponsor:

SIGDA

FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Cakir BMalik S(2019)Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit EmbeddingsACM Transactions on Design Automation of Electronic Systems10.1145/332908124:5(1-19)Online publication date: 12-Jun-2019
https://dl.acm.org/doi/10.1145/3329081
Cakir BMalik S(2018)Reverse Engineering Digital ICs through Geometric Embedding of Circuit GraphsACM Transactions on Design Automation of Electronic Systems10.1145/319312123:4(1-19)Online publication date: 18-Jul-2018
https://dl.acm.org/doi/10.1145/3193121
Mukherjee RLiu SMemik SMondal S(2008)A high-level clustering algorithm targeting dual Vdd FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139196513:4(1-20)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391965
Liu HWong D(2006)Network-flow-based multiway partitioning with area and pin constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.67363217:1(50-59)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.673632
Fang WWu A(2006)A hierarchical functional structuring and partitioning approach for multiple-FPGA implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66268016:10(1188-1195)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.662680
Mukherjee RMemik S(2004)Power-Driven Design PartitioningField Programmable Logic and Application10.1007/978-3-540-30117-2_75(740-750)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30117-2_75
Vemuri RGovindarajan SOuaiss IKaul MSrinivasan VRadhakrishnan SSundaraman SGanesan SPandey ALakshmikanthan P(2001)Automated design synthesis and partitioning for adaptive reconfigurable hardwareHardware implementation of intelligent systems10.5555/570780.570781(3-52)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.5555/570780.570781
Srinivasan VGovindarajan SVemuri R(2001)Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9208299:1(140-159)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1109/92.920829
Kaul MVemuri R(2000)Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable SystemsField-Programmable Custom Computing Technology: Architectures, Tools, and Applications10.1007/978-1-4615-4417-3_5(55-83)Online publication date: 2000
https://doi.org/10.1007/978-1-4615-4417-3_5
Liu HZhu KWong DCong JKaptanoglu S(1998)Circuit partitioning with complex resource constraints in FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275122(77-84)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1145/275107.275122
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SPECTRAL-BASED MULTI-WAY FPGA PARTITIONING

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