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Building a Java™ Virtual Machine for Non-Cache-Coherent Many-core Architectures

Published: 29 August 2016 Publication History

Abstract

This work presents the key challenges that Java Virtual Machines (JVMs) implementers face when targeting future non-cache-coherent architectures. It discusses the techniques used to overcome these challenges by distributed JVMs in the literature, and examines their applicability on future non-cache-coherent architectures. It presents new algorithms for software caching, monitor management, and thread scheduling, that take advantage of the hierarchical nature of future non-cache-coherent architectures with coherent-islands. It also builds a proof-of-concept JVM that runs on a 512-core, non-cache-coherent, many-core prototype and present early evaluation results for parts of the proposed algorithms.

References

[1]
https://github.com/CARV-ICS-FORTH/disquawk.
[2]
U. A. Acar, A. Chargueraud, and M. Rainey. Scheduling Parallel Programs by Work Stealing with Private Deques. In PPoPP, 2013.
[3]
G. Antoniu, L. Bougé, P. J. Hatcher, M. MacBeth, K. McGuigan, and R. Namyst. The Hyperion system: Compiling multithreaded Java bytecode for distributed execution. Parallel Computing, 27(10), 2001.
[4]
Y. Aridor, M. Factor, and A. Teperman. cJVM: A Single System Image of a JVM on a Cluster. In ICPP, 1999.
[5]
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In PACT, 2008.
[6]
R. D. Blumofe and C. E. Leiserson. Scheduling Multithreaded Computations by Work Stealing. J. ACM, 46(5):720--748, 1999.
[7]
R. L. Bocchino, Jr., V. S. Adve, D. Dig, S. V. Adve, S. Heumann, R. Komuravelli, J. Overbey, P. Simmons, H. Sung, and M. Vakilian. A Type and Effect System for Deterministic Parallel Java. In OOPSLA, 2009.
[8]
N. P. Carter, A. Agrawal, S. Borkar, R. Cledat, H. David, D. Dunning, J. B. Fryman, I. Ganev, R. A. Golliver, R. C. Knauerhase, R. Lethin, B. Meister, A. K. Mishra, W. R. Pinfold, J. Teller, J. Torrellas, N. Vasilache, G. Venkatesh, and J. Xu. Runnemede: An architecture for Ubiquitous High-Performance Computing. In HPCA, 2013.
[9]
D. Chase and Y. Lev. Dynamic Circular Work-stealing Deque. In SPAA, 2005.
[10]
B. Choi, R. Komuravelli, H. Sung, R. Smolinski, N. Honarmand, S. V. Adve, V. S. Adve, N. P. Carter, and C.-T. Chou. DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism. In PACT', 2011.
[11]
J. Dinan, D. B. Larkins, P. Sadayappan, S. Krishnamoorthy, and J. Nieplocha. Scalable Work Stealing. In SC, 2009.
[12]
Y. Durand, P. Carpenter, S. Adami, A. Bilas, D. Dutoit, A. Farcy, G. Gaydadjiev, J. Goodacre, M. Katevenis, M. Marazakis, E. Matus, I. Mavroidis, and J. Thomson. EUROSERVER: Energy Efficient Node for European Micro-Servers. In DSD, 2014.
[13]
J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, F. Pailet, S. Jain, T. Jacob, S. Yada, S. Marella, P. Salihundam, V. Erraguntla, M. Konow, M. Riepen, G. Droege, J. Lindemann, M. Gries, T. Apel, K. Henriss, T. Lund-Larsen, S. Steibl, S. Borkar, V. De, R. Van der Wijngaart, and T. Mattson. A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. In ISSCC, 2010.
[14]
Y. hun Eom, S. Yang, J. C. Jenista, and B. Demsky. DOJ: Dynamically Parallelizing Object-Oriented Programs. In PPoPP, 2012.
[15]
L. Lamport. Time, clocks, and the ordering of events in a distributed system. Commun. ACM, 21(7), 1978.
[16]
D. Lea. The JSR-133 cookbook for compiler writers, 2008.
[17]
S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou, D. Tsaliagkos, M. Katevenis, D. Pnevmatikatos, and D. Nikolopoulos. Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. In FCCM, 2012.
[18]
J. Manson, W. Pugh, and S. V. Adve. The Java Memory Model. In POPL, 2005.
[19]
M. M. K. Martin, M. D. Hill, and D. J. Sorin. Why On-chip Cache Coherence is Here to Stay. Commun. ACM, 55(7), 2012.
[20]
R. McIlroy and J. Sventek. Hera-JVM: A Runtime System for Heterogeneous Multi-core Architectures. In OOPSLA, 2010.
[21]
L. G. Menezo, V. Puente, and J. A. Gregorio. The Case for a Scalable Coherence Protocol for Complex On-chip Cache Hierarchies in Many Core Systems. In PACT, 2013.
[22]
S.-J. Min, C. Iancu, and K. Yelick. Hierarchical work stealing on manycore clusters. In PGAS, 2011.
[23]
S.-c. Multiprocessor, A. Noll, A. Gal, and M. Franz. CellVM: A homogeneous virtual machine runtime system for a heterogeneous single-chip multiprocessor. Workshop on Cell Systems and Applications, 2008.
[24]
T. Peierls, B. Goetz, J. Bloch, J. Bowbeer, D. Lea, and D. Holmes. Java concurrency in practice. 2006.
[25]
D. Pham, S. Asano, M. Bolliger, M. Day, H. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, et al. The design and implementation of a first-generation CELL processor--a multi-core SoC. In ICICDT, 2005.
[26]
D. Simon, C. Cifuentes, D. Cleal, J. Daniels, and D. White. Java™on the Bare Metal of Wireless Sensor Devices: The Squawk Java Virtual Machine. In VEE, 2006.
[27]
L. A. Smith, J. M. Bull, and J. Obdrzálek. A Parallel Java Grande Benchmark Suite. In SC, 2001.
[28]
Q. Yang, J. Fu, R. Poss, and C. Jesshope. On-chip Traffic Regulation to Reduce Coherence Protocol Cost on a Microthreaded Many-core Architecture with Distributed Caches. ACM Trans. Embed. Comput. Syst., 13(3s), 2014.
[29]
F. S. Zakkak and P. Pratikakis. JDMM: A Java Memory Model for Non-cache-coherent Memory Architectures. In ISMM, 2014.
[30]
G. Zheng, E. Meneses, A. Bhatele, and L. V. Kale. Hierarchical load balancing for Charm++ applications on large supercomputers. In ICPPW, 2010.
[31]
W. Zhu, C.-L. Wang, and F. C. M. Lau. JESSICA2: A Distributed Java Virtual Machine with Transparent Thread Migration Support. In CLUSTER, 2002.

Cited By

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  • (2023)Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad MemoriesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582020(46-58)Online publication date: 25-Mar-2023

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Published In

cover image ACM Other conferences
JTRES '16: Proceedings of the 14th International Workshop on Java Technologies for Real-Time and Embedded Systems
August 2016
56 pages
ISBN:9781450348003
DOI:10.1145/2990509
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 August 2016

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Author Tags

  1. Java Virtual Machine
  2. Many-core
  3. Non Coherent Memory

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  • Refereed limited

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JTRES '16

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JTRES '16 Paper Acceptance Rate 5 of 6 submissions, 83%;
Overall Acceptance Rate 50 of 70 submissions, 71%

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View all
  • (2023)Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad MemoriesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582020(46-58)Online publication date: 25-Mar-2023

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