research-article

RRAM based learning acceleration

Authors:

Huazhong YangAuthors Info & Claims

CASES '16: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Article No.: 9, Pages 1 - 2

https://doi.org/10.1145/2968455.2981124

Published: 01 October 2016 Publication History

Abstract

Deep Learning (DL) is becoming popular in a wide range of domains. Many emerging applications, ranging from image and speech recognition to natural language processing and information retrieval, rely heavily on deep learning techniques, especially the Neural Networks (NNs). NNs have led to great advances in recognition accuracy compared with other traditional methods in recent years. NN-based methods demand much more computation and memory resource, and therefore a number of NN accelerators have been proposed on CMOS-based platforms, such as FPGA and GPU [1]. However, it becomes more and more difficult to obtain substantial power efficiency and gains directly through the scaling down of traditional CMOS technique. Meanwhile, the large data amount in DL applications also meets an ever-increasing "memory wall" challenge because of the efficiency of von Neumann architecture. Consequently, there is a growing research interest of exploring emerging nano-devices and new computing architectures to further improve power efficiency [2].

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Cited By

Rahimifard LShylendra ANasrin SLiu SSangwan VHersam MTrivedi A(2022)Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbarsFrontiers in Electronic Materials10.3389/femat.2022.9504872Online publication date: 8-Aug-2022
https://doi.org/10.3389/femat.2022.950487
Berthou GDelizy TMarquet KRisset TSalagnac G(2019)Sytare: a Lightweight Kernel for NVRAM-Based Transiently-Powered SystemsIEEE Transactions on Computers10.1109/TC.2018.2889080(1-1)Online publication date: 2019
https://doi.org/10.1109/TC.2018.2889080

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CASES '16: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems

October 2016

187 pages

ISBN:9781450344821

DOI:10.1145/2968455

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 October 2016

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National Natural Science Foundation of China
973 project
Tsinghua University Initiative Scientific Research Program

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ESWEEK'16

ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK

October 1 - 7, 2016

Pennsylvania, Pittsburgh

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Cited By

Rahimifard LShylendra ANasrin SLiu SSangwan VHersam MTrivedi A(2022)Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbarsFrontiers in Electronic Materials10.3389/femat.2022.9504872Online publication date: 8-Aug-2022
https://doi.org/10.3389/femat.2022.950487
Berthou GDelizy TMarquet KRisset TSalagnac G(2019)Sytare: a Lightweight Kernel for NVRAM-Based Transiently-Powered SystemsIEEE Transactions on Computers10.1109/TC.2018.2889080(1-1)Online publication date: 2019
https://doi.org/10.1109/TC.2018.2889080

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