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Very long instruction work architectures and the ELI-512

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Joseph A. FisherAuthors Info & Claims

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

Pages 263 - 273

https://doi.org/10.1145/285930.285985

Published: 01 August 1998 Publication History

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References

[1]

A.V. Aho and J. D. Ullman. Principles of Compiler Design. Addison-Wesley, 1977.

Digital Library

Google Scholar

[2]

Dazgupta, S. The Organization of Microprogram Stores. ACM Cornp. Surv. 11(1):39-65, Mar. 1979.

Digital Library

Google Scholar

[3]

J.A. Fisher. An effective packing method for use with 2n-way jump instruction hardware. In 13th annual microproframminf workshop, pages 64-75. ACM Special Interest Group on Micropmgramming, November 1980.

Crossref

Google Scholar

[4]

J.A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers c-30(7):478-490, July 1981.

Google Scholar

[5]

C.C. Foster and E. M. Riseman. Percolation of code to enhance parallel dispatching and execution. IEEE Transactions on Computers 21(12):1411-1415, December 1972.

Digital Library

Google Scholar

[6]

T.R. Gross and J. L. Hennemy. Optimizing Delayed Branches. In 15th annual workshop on mieroproffammin g, pages 114-120. ACM Special interest Group on Mieroprogramming, October 1982.

Crossref

Google Scholar

[7]

J. Henne~y, N. Jouppi, S. Przbyeki, C. Rowen, T. Gram, F. Baskett, and J. Gill. MIPS" A Microprocessor Architecture. In 15th annual tvork~hop on mieroproframmino, pages 17-22. ACM Special Interest Group on Microprogramming, October 1982.

Crossref

Google Scholar

[8]

D. Jacobe, J. Prin~, P. Siegel and K. Wilson. Monte carlo techniques in code optimization. In 15th annual workshop on microproframming, pages 143-148. ACM Special interest Group aa Microprogramming, October 1982.

Crossref

Google Scholar

[9]

Aiexandru Nicolau ud Jmeph A. Fisher. Using u oracle to measure parallelism in single instruction stream programs. In IJth annual microprogramminf workshop, pages 171-182. ACM Special Interest Group on Microprogramming, October 1981.

Crossref

Google Scholar

[10]

D.A. Padua, D. J. Kuck, and D. H. Lawrie. High speed multiprocemors and compilation techniques. 1 IEEE Transactions on Computers 29{9):763-776, September 1980.

Google Scholar

[11]

D.A. Patterson, K. Lew, and It. Tuck. Towards an efficient machine-independent language for microprogramming. In l~h annual microproframminf workshop, pages 22-35. ACM Special Interest Group on Micropmgramming, 1979.

Digital Library

Google Scholar

[12]

D.A. Patterson and C. H. Sequin. A VLSI RISC. Computer 15(9):8-21, SEPT 1982.

Digital Library

Google Scholar

[13]

E.M. Riseman and C. C. Foster. The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers 21(12):1405-1411, December 1972.

Digital Library

Google Scholar

[14]

G.S. Tjaden and M. J. Flynn. Detection and parallel execution of independent instructions. IEEE Transactions on Computers 19(10):889-895, October 1970.

Digital Library

Google Scholar

[15]

Tokoro, M. ; Takizuka, T. ; Tamers E. and Yamaura, I. Towards an Efficient Machlne-lndependent Language for Mieropmgramming. In llth Annual A6croproffamminl Workshop, pages 41-50. SIGMICRO, 1978.

Digital Library

Google Scholar

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Tran KJimborean ACarlson TKoukos KSjälander MKaxiras S(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresACM SIGPLAN Notices10.1145/3296979.319239353:4(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192393
Tran KJimborean ACarlson TKoukos KSjälander MKaxiras SFoster JGrossman D(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192393(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192393
Nagpal RSrikant Y(2011)Compiler-assisted power optimization for clustered VLIW architecturesParallel Computing10.1016/j.parco.2010.08.00537:1(42-59)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1016/j.parco.2010.08.005
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Published In

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

August 1998

546 pages

ISBN:1581130589

DOI:10.1145/285930

Editor:
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1998

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ISCA98

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SIGARCH
IEEE-CS\TCCA

ISCA98: International Symposium on Computer Architecture

June 27 - July 2, 1998

Barcelona, Spain

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

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Cited By

View all

Tran KJimborean ACarlson TKoukos KSjälander MKaxiras S(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresACM SIGPLAN Notices10.1145/3296979.319239353:4(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192393
Tran KJimborean ACarlson TKoukos KSjälander MKaxiras SFoster JGrossman D(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192393(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192393
Nagpal RSrikant Y(2011)Compiler-assisted power optimization for clustered VLIW architecturesParallel Computing10.1016/j.parco.2010.08.00537:1(42-59)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1016/j.parco.2010.08.005
Mohamed NBotros NAlweh M(2009)Cache Memory Energy Exploitation in VLIW ArchitecturesAdvanced Techniques in Computing Sciences and Software Engineering10.1007/978-90-481-3660-5_60(351-355)Online publication date: 15-Dec-2009
https://doi.org/10.1007/978-90-481-3660-5_60
Kulkarni MPingali KWalter BRamanarayanan GBala KChew L(2007)Optimistic parallelism requires abstractionsACM SIGPLAN Notices10.1145/1273442.125075942:6(211-222)Online publication date: 10-Jun-2007
https://dl.acm.org/doi/10.1145/1273442.1250759
Kulkarni MPingali KWalter BRamanarayanan GBala KChew LFerrante JMcKinley K(2007)Optimistic parallelism requires abstractionsProceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/1250734.1250759(211-222)Online publication date: 15-Jun-2007
https://dl.acm.org/doi/10.1145/1250734.1250759
Nagpal RSrikant Y(2007)Register File Energy Optimization for Snooping Based Clustered VLIW Architectures19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)10.1109/SBAC-PAD.2007.35(161-168)Online publication date: Oct-2007
https://doi.org/10.1109/SBAC-PAD.2007.35
Nagpal RSrikant Y(2007)Pragmatic integrated scheduling for clustered VLIW architecturesSoftware: Practice and Experience10.1002/spe.82638:3(227-257)Online publication date: 29-May-2007
https://doi.org/10.1002/spe.826
Wen MWu NLi HZhang C(2004)Multiple-Dimension Scalable Adaptive Stream ArchitectureAdvances in Computer Systems Architecture10.1007/978-3-540-30102-8_17(199-211)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30102-8_17

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Very Long Instruction Word architectures and the ELI-512

Increasing the instruction fetch rate via block-structured instruction set architectures

Block enlargement optimizations for increasing the instruction fetch rate in block-structured instruction set architectures