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SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips

Published: 29 March 2015 Publication History

Abstract

The chip-level design problem is critical in pin-constrained electrowetting-on-dielectric (EWOD) biochips, which not only affects the number of control pins and PCB routing layers from the manufacturing cost point of view, but also determines the functional reliability induced by excessive applied voltage. Existing works either greedily minimize the number of control pins with degraded routability, or disregard the differences in driving voltages on the electrodes, where the trapped charge due to excessive applied voltage causes significant reliability issue. This paper presents the first SVM-based classifier for electrode addressing in chip-level design stage, which simultaneously optimizes the number of control pins, routability, as well as reliability. Experimental results on both real-life chips and synthesized benchmarks show that, compared with the state-of-the-art method, the SVM-based electrode addressing method obtains significant improvements in both routability and reliability.

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  1. SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips

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    cover image ACM Conferences
    ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design
    March 2015
    204 pages
    ISBN:9781450333993
    DOI:10.1145/2717764
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 29 March 2015

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    Author Tags

    1. chip-level design
    2. digital microfluidic biochips
    3. electrode addressing
    4. electrowetting-on-dielectric
    5. svm

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    March 29 - April 1, 2015
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    • (2024)Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337065243:8(2465-2478)Online publication date: Aug-2024
    • (2024)Advancement with digital microfluidic biochips towards sustainability and secured outcome: a comprehensive survey on specific design metricsDiscover Electronics10.1007/s44291-024-00018-x1:1Online publication date: 5-Aug-2024
    • (2020)Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289482039:3(613-625)Online publication date: Mar-2020
    • (2020)Pin Addressing Method Based on an SVM With a Reliability Constraint in Digital Microfluidic BiochipsIEEE Access10.1109/ACCESS.2020.30349458(199792-199802)Online publication date: 2020
    • (2018)Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.274800337:6(1157-1170)Online publication date: Jun-2018
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    • (2017)Smart Microfluidic Biochips: Cyberphysical Sensor Integration for Dynamic Error RecoverySmart Sensors at the IoT Frontier10.1007/978-3-319-55345-0_3(23-71)Online publication date: 31-May-2017
    • (2016)Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic BiochipsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254167124:11(3345-3358)Online publication date: 1-Nov-2016

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