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Data prefetching on the HP PA-8000

Authors:

Vatsa Santhanam,

Edward H. Gornish,

Wei-Chung HsuAuthors Info & Claims

ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture

Pages 264 - 273

https://doi.org/10.1145/264107.264208

Published: 01 May 1997 Publication History

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Abstract

Memory latency is a major issue for many modern microprocessor based systems, including the Hewlett-Packard PA-8000. Due to its fast clock rate and wide issue capability, cache misses in the PA-8000 are very expensive. The PA-8000 combines out-of-order execution with multiple outstanding memory requests to tolerate memory latency; however, this approach has its limitations. In order to substantially reduce much of the memory latency penalty, the PA-8000 uses software-based data cache prefetching. In this paper, we discuss the implementation of the data prefetch generation algorithm in the Hewlett-Packard Precision Architecture (HP-PA) compiler. We present performance results for SPECfp95 on a PA-8000 system that show speedups, due to data prefetching, of up to 100%.

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Cited By

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Mehta SFang ZZhai AYew PBode AGerndt MStenström PRauchwerger LMiller BSchulz M(2014)Multi-stage coordinated prefetching for present-day processorsProceedings of the 28th ACM international conference on Supercomputing10.1145/2597652.2597660(73-82)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2597652.2597660
Marin GMcCurdy CVetter JMalony ANemirovsky MMidkiff S(2013)Diagnosis and optimization of application prefetching performanceProceedings of the 27th international ACM conference on International conference on supercomputing10.1145/2464996.2465014(303-312)Online publication date: 10-Jun-2013
https://dl.acm.org/doi/10.1145/2464996.2465014
August DRaman E(2009)Optimizations for Memory HierarchiesThe Compiler Design Handbook10.1201/9781420043839.ch5(5-1-5-30)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch5
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Data prefetching on the HP PA-8000

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Data prefetching on the HP PA-8000
Special Issue: Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97)

Memory latency is a major issue for many modern microprocessor based systems, including the Hewlett-Packard PA-8000. Due to its fast clock rate and wide issue capability, cache misses in the PA-8000 are very expensive. The PA-8000 combines out-of-order ...
The HP PA-8000 RISC CPU

The PA-8000 RISC CPU is the first implementation of a new generation of microprocessors from Hewlett-Packard Company. The processor was designed for high-end systems and to support the new 64-bit PA-RISC 2.0 architecture. The aggressive four-way ...
Increasing hardware data prefetching performance using the second-level cache

Techniques to reduce or tolerate large memory latencies are critical for achieving high processor performance. Hardware data prefetching is one of the most heavily studied solutions, but it is essentially applied to first-level caches where it can ...

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Published In

ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture

June 1997

350 pages

ISBN:0897919017

DOI:10.1145/264107

Chairmen:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan

ACM SIGARCH Computer Architecture News Volume 25, Issue 2
Special Issue: Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97)
May 1997
349 pages
ISSN:0163-5964
DOI:10.1145/384286
Editors:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1997

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ISCA97: International Conference on Computer Architecture

June 1 - 4, 1997

Colorado, Denver, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Citations

Cited By

View all

Mehta SFang ZZhai AYew PBode AGerndt MStenström PRauchwerger LMiller BSchulz M(2014)Multi-stage coordinated prefetching for present-day processorsProceedings of the 28th ACM international conference on Supercomputing10.1145/2597652.2597660(73-82)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2597652.2597660
Marin GMcCurdy CVetter JMalony ANemirovsky MMidkiff S(2013)Diagnosis and optimization of application prefetching performanceProceedings of the 27th international ACM conference on International conference on supercomputing10.1145/2464996.2465014(303-312)Online publication date: 10-Jun-2013
https://dl.acm.org/doi/10.1145/2464996.2465014
August DRaman E(2009)Optimizations for Memory HierarchiesThe Compiler Design Handbook10.1201/9781420043839.ch5(5-1-5-30)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch5
Galazin AStupachenko EShlykov S(2008)A software instruction prefetching method in architectures with static schedulingProgramming and Computing Software10.1134/S036176880801006434:1(49-53)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1134/S0361768808010064
Zou QLi XZhang L(2008)Runtime engine for dynamic profile guided stride prefetchingJournal of Computer Science and Technology10.1007/s11390-008-9159-223:4(633-643)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11390-008-9159-2
Yang CYang XXue J(2005)Improving the performance of GCC by exploiting IA-64 architectural featuresProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_20(236-251)Online publication date: 24-Oct-2005
https://dl.acm.org/doi/10.1007/11572961_20
Cahoon BMcKinley K(2005)Recurrence analysis for effective array prefetching in JavaConcurrency and Computation: Practice and Experience10.1002/cpe.85117:5-6(589-616)Online publication date: 22-Feb-2005
https://doi.org/10.1002/cpe.851
Batten CKrashinsky RGerding SAsanovic K(2004)Cache Refill/Access Decoupling for Vector MachinesProceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2004.9(331-342)Online publication date: 4-Dec-2004
https://dl.acm.org/doi/10.1109/MICRO.2004.9
Iwamoto YSuga KOotsu KYokota TBaba T(2003)Receiving message prediction methodParallel Computing10.1016/j.parco.2003.05.00529:11-12(1509-1538)Online publication date: 1-Nov-2003
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Hu ZKaxiras SMartonosi MPatt YGrunwald DSkadron K(2002)Timekeeping in the memory systemProceedings of the 29th annual international symposium on Computer architecture10.5555/545215.545239(209-220)Online publication date: 25-May-2002
https://dl.acm.org/doi/10.5555/545215.545239
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Data prefetching on the HP PA-8000

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