research-article

The locality-aware adaptive cache coherence protocol

Authors:

Srinivas DevadasAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 41, Issue 3

Pages 523 - 534

https://doi.org/10.1145/2508148.2485967

Published: 23 June 2013 Publication History

Abstract

Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient shared memory cache coherence protocol that enables seamless adaptation between private and logically shared caching of on-chip data at the fine granularity of cache lines. Our data-centric approach relies on in-hardware yet low-overhead runtime profiling of the locality of each cache line and only allows private caching for data blocks with high spatio-temporal locality. This allows us to better exploit the private caches and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. On a set of parallel benchmarks, our low-overhead locality-aware mechanisms reduce the overall energy by 25% and completion time by 15% in an NoC-based multicore with the Reactive-NUCA on-chip cache organization and the ACKwise limited directory-based coherence protocol.

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Cited By

Holtryd NManivannan MStenstrom PPericas M(2020)DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00066(578-589)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00066
Liu YSun X(2019)LPM: A Systematic Methodology for Concurrent Data Access Pattern Optimization from a Matching PerspectiveIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2019.291257330:11(2478-2493)Online publication date: 9-Oct-2019
https://dl.acm.org/doi/10.1109/TPDS.2019.2912573
Cabrera AChamberlain RBeard J(2019)Multi-spectral Reuse Distance: Divining Spatial Information from Temporal Data2019 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC.2019.8916398(1-8)Online publication date: Sep-2019
https://doi.org/10.1109/HPEC.2019.8916398
Show More Cited By

Index Terms

The locality-aware adaptive cache coherence protocol
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 41, Issue 3

ICSA '13

June 2013

666 pages

ISSN:0163-5964

DOI:10.1145/2508148

Issue’s Table of Contents

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture
June 2013
686 pages
ISBN:9781450320795
DOI:10.1145/2485922
General Chair:
Avi Mendelson
Technion

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 2013

Published in SIGARCH Volume 41, Issue 3

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Cited By

Holtryd NManivannan MStenstrom PPericas M(2020)DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00066(578-589)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00066
Liu YSun X(2019)LPM: A Systematic Methodology for Concurrent Data Access Pattern Optimization from a Matching PerspectiveIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2019.291257330:11(2478-2493)Online publication date: 9-Oct-2019
https://dl.acm.org/doi/10.1109/TPDS.2019.2912573
Cabrera AChamberlain RBeard J(2019)Multi-spectral Reuse Distance: Divining Spatial Information from Temporal Data2019 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC.2019.8916398(1-8)Online publication date: Sep-2019
https://doi.org/10.1109/HPEC.2019.8916398
Sembrant AHagersten EBlack-Schaffer D(2016)Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753269(117-124)Online publication date: Oct-2016
https://doi.org/10.1109/ICCD.2016.7753269
Liu YSun X(2015)LPMProceedings of the 2015 44th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2015.97(879-888)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/ICPP.2015.97
Joshi ARamasubramanian N(2015)Comparison of significant issues in multicore cache coherenceProceedings of the 2015 International Conference on Green Computing and Internet of Things (ICGCIoT)10.1109/ICGCIoT.2015.7380439(108-112)Online publication date: 8-Oct-2015
https://dl.acm.org/doi/10.1109/ICGCIoT.2015.7380439
Zhang AGoens AOswald NGrosser TSorin DNagarajan V(2024)PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency ModelProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676889(1-13)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676889
Alsop JNa WSinclair MGrayson SAdve S(2022)A Case for Fine-grain Coherence Specialization in Heterogeneous SystemsACM Transactions on Architecture and Code Optimization10.1145/353081919:3(1-26)Online publication date: 22-Aug-2022
https://dl.acm.org/doi/10.1145/3530819
Li CJiang FChen SZhang JLiu YFu YXu JMitra TYoung EXiong J(2022)Accelerating Cache Coherence in Manycore Processor through Silicon Photonic ChipletProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549338(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549338
Ibrahim MKayiran OEckert YLoh GJog ASarkar VKim H(2020)Analyzing and Leveraging Shared L1 Caches in GPUsProceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques10.1145/3410463.3414623(161-173)Online publication date: 30-Sep-2020
https://dl.acm.org/doi/10.1145/3410463.3414623
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