Improving cache performance with balanced tag and data paths
Abstract
There are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. In both direct-mapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In this paper, we propose a path balancing technique help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6% to 28% are possible.
References
[1]
A. Agarwal, and S. Pudar, "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches," Proc. of ~Oth Int'l Syrup. on Computer Architecture, May 1993, pp. 179-190.
[2]
J.-L. Baer, and W.-H. Wang, "On the Inclusion Property for Multi-level Cache Hierarchies," Proc. of 15th Int'l Syrup. on Computer Architecture, May 1988, pp. 73-80.
[3]
P. Bannon, and J. Keller, "Internal Architecture of AI- pha 21164 Microprocessor," Proc. COMPCON'95, Mar. 95, pp. 79-87.
[4]
T. Chappell, et.al., "A 2ns Cycle, 3.8ns Access 512KB CMOS ECL RAM with a Fully Pipelined Architecture," IEEE Journal of Solid-State Circuits, Vol. 26(11), Nov. 1991, pp. 1577-1585.
[5]
J. Gee, M. Hill, D. Pnevmatikatos, and A. Smith, "Cache Performance of the SPEC92 Benchmark Suite," IEEE Micro, Vol. 13(4), Aug. 1993, pp. 17-27.
[6]
J. Goodman, "Coherency for Multiprocessor Virtual Address Caches," Proc. of 2nd Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, Oct. 1987, pp. 72-81.
[7]
D. Grccnlcy et al., "UltraSPARG: The Next Generation Superscalar 64-bit SPARC," Proc. COMPCON'95, Mar. 95, pp. 442-451.
[8]
J. Hennessy, and D. Patterson, "Computer Architecture, A Quantitative Approach," 2nd-Edition, Morgan- Kaufmann, 1996.
[9]
M. Hill "A Case for Direct-Mapped Caches," IEEE Computer, Vol. 21(12), Dec. 1988, pp. 25-40.
[10]
HSPICE User's Manual, Meta-Software Inc, 1992.
[11]
K. Hua, L. Liu, and J.-K. Peir, "Designing High Performance Processors Using Real-Address Prediction," IEEE Transactions on Computers, C-42(9), Sep. 1993, pp. 1146-1151.
[12]
D. Hunt, "Advanced Performance Features of the 64-bit PA-8000," Proc. COMPCON'95, Mar. 95, pp. 123-128.
[13]
N. Jouppi, and S. Wilton "Tradeoffs in Two-Level On- Chip Caching," Proc. of ~1st Int'l Syrup. on Computer Architecture, Apr. 1994, pp. 34-45.
[14]
D. Levitan, T. Thomas, and P. Tu, "The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor," Proc. COMPCON'95, Mar. 1995, pp. 285-291.
[15]
MIPS Technologies Inc. "R10000 Microprocessor," Product Overview, Oct. 1994.
[16]
J. Mulder, N. Quach, and M. Flynn, "An Area Model for On-Chip Memories and its Application," IEEE Journal of Sol~d-State Circuits, Feb. 1991, Vol. 26(2), pp. 98-106.
[17]
K. Olukotun, T. Mudge, and R. Brown, "Performance Optimization of Pipelined Primary caches," Proc. of 19th Int'l Symp. on Computer Arch,tecture, May 1992, pp. 181-190.
[18]
S. Przybylski, M. Horowitz, and J. Hennessy, "Characteristics of Performance-Optimal Multi-Level Cache Hierarchies," Proc. of 16th Int'l Syrup. on Computer Architecture, May. 1989, pp. 114-121.
[19]
A. Seznec, :'Don't use the page number, but a pointer to it," Proc. of ~3rd Int'l Syrup. on Computer Architecture, May 1996, pp. 104-113.
[20]
A. Smith, "Cache Memories," Computing Surveys, 14(4), Sep. 1982, pp. 473-530.
[21]
K. So, and R. Rechtschaffen, "Cache Operations by MRU Change," IEEE Trans. on Computers, C-37(6), Jun. 1988, pp. 700-709.
[22]
System Performance Evaluation Cooperative, SPEC News-letter, 1990.
[23]
TPC Council, "TPC Benchmark C, Standard Specificat;ion, Rev. 3.0," Feb. 1995.
[24]
T. Wads, $. Rajan, and S. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories," IEEE Journal of Solid-State Circuits, Vol. 27(8), Aug. 1992, pp. 1147-1156.
[25]
S. Wilton, and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," DEC WRL Research Report 93//5, Jul. 1994.
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- Improving cache performance with balanced tag and data paths
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Improving cache performance with balanced tag and data paths
ASPLOS VII: Proceedings of the seventh international conference on Architectural support for programming languages and operating systemsThere are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/...
Improving cache performance with balanced tag and data paths
There are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/...
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Published In
Sept. 1996
273 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/248209
- Chairmen:
- Bill Dally,
- Susan Eggers
Copyright © 1996 ACM.
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Publication History
Published: 01 September 1996
Published in SIGPLAN Volume 31, Issue 9
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