research-article

A methodology for the early exploration of design rules for multiple-patterning technologies

Authors:

Rani S. Ghaida,

Parag Kulkarni,

Puneet GuptaAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 50 - 56

https://doi.org/10.1145/2429384.2429395

Published: 05 November 2012 Publication History

Abstract

Double/Multiple-patterning (DP/MP) lithography in a multiple litho-etch steps process is a favorable solution for technology scaling to the 20nm node and below. Mask-assignment conflicts represent the biggest challenge for MP and limiting them through design rules is crucial for the adoption of MP technology. In this paper, we offer a methodology for the early evaluation and exploration of layout and MP rules intended for speeding up the rules-development cycle. Using a novel wiring-estimation method, we create layout estimates with fine-grained congestion prediction. MP-conflicts are then predicted using a machine-learning approach. In this work, we demonstrate the use of the method for double-patterning lithography in litho-etch-litho-etch process; the methodology is more general, however, and can be applied for other multiple-patterning technologies including tripe/multiple-patterning with multiple litho-etch steps, self-aligned double patterning (SADP), and directed self-assembly. Results of testing the methodology on standard-cell layouts show an 81% accuracy in DP-conflicts prediction. The methodology was then used to explore DP and layout rules and investigate their effects on DP-compatibility and layout area. The methodology allows for rules optimization; for example, pushing the minimum tip-to-side same-color spacing rule value from 1.7x to 1.5x the minimum side-to-side spacing design rule (i.e., from 110nm down to 90nm) would more than double the number of DP-compatible cells in the library.

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Cited By

Paul SBanerjee PSur‐Kolay S(2021)A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segmentsIET Circuits, Devices & Systems10.1049/cds2.1202815:4(310-329)Online publication date: 29-Mar-2021
https://doi.org/10.1049/cds2.12028
Jo KAhn SKim TChoi KShin Y(2018)Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completionProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201727(500-506)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201727
Jo KAhn SKim TChoi K(2018)Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297373(500-506)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297373
Show More Cited By

Index Terms

A methodology for the early exploration of design rules for multiple-patterning technologies
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Published In

cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Paul SBanerjee PSur‐Kolay S(2021)A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segmentsIET Circuits, Devices & Systems10.1049/cds2.1202815:4(310-329)Online publication date: 29-Mar-2021
https://doi.org/10.1049/cds2.12028
Jo KAhn SKim TChoi KShin Y(2018)Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completionProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201727(500-506)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201727
Jo KAhn SKim TChoi K(2018)Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297373(500-506)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297373
Hamouda AAbdelghany H(2016)Combining mask and OPC process verification for improved wafer patterning and yieldPhotomask Technology 201610.1117/12.2246563(99852A)Online publication date: 26-Sep-2016
https://doi.org/10.1117/12.2246563
Hamouda AAnis MKarim K(2016)Model-Based Initial Bias (MIB)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251290835:10(1630-1639)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2512908
Duan YSu XChen YSu YWei YShao FZhang RLei J(2016)Design technology co-optimization for N14 Metal1 layer2016 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC.2016.7463980(1-4)Online publication date: Mar-2016
https://doi.org/10.1109/CSTIC.2016.7463980
Paul SBanerjee PSur-Kolay S(2015)Flare reduction in EUV Lithography by perturbation of wire segments2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2015.7314383(7-12)Online publication date: Oct-2015
https://doi.org/10.1109/VLSI-SoC.2015.7314383
Ghaida RGupta PMacii E(2013)Role of design in multiple patterningProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485366(314-319)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485366

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