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New test data decompressor for low power applications

Published: 04 June 2007 Publication History

Abstract

The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression ratios.

References

[1]
B. Benware, C. Schuermyer, S. Ranganathan, R. Madge, P. Krishnamurthy, N. Tamarapalli, K.-H. Tsai, and J. Rajski, "Impact of multiple-detect test patterns on product quality." Proc. ITC, pp. 1031--1040, 2003.
[2]
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "A gated clock scheme for low power scan testing of logic ICs or embedded cores." Proc. ATS, pp. 253--258, 2001.
[3]
Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, "Power driven chaining of flip-flops in scan architecture." Proc. ITC, pp. 796--803, 2002
[4]
K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, "Minimizing power consumption in scan testing: pattern generation and DFT techniques." Proc. ITC, pp. 355--364, 2004.
[5]
S. Chakravarty and V. P. Dabholkar, "Two techniques for minimizing power dissipation in scan circuits during test applications." Proc. ATS, pp. 324--329, 1994.
[6]
A. Chandra and K. Chakrabarty, "Combining low-power scan testing and test data compression for system-on-a-chip," Proc. DAC, pp. 166--169, 2001.
[7]
A. Chandra and K. Chakrabarty, "Reduction of SOC test data volume, scan power and testing time using alternating run-length codes," Proc. DAC, pp. 673--678, 2002.
[8]
A. Chandra and K. Chakrabarty, "Low-power scan testing and test data compression for system-on-a-chip," IEEE Trans. CAD, vol. 21, pp. 597--604, May 2002.
[9]
M. Chiu and J. C.-M. Li, "Jump scan: a DFT technique for low power testing," Proc. VTS, pp. 277--282, 2005.
[10]
R. M. Chou, K. K. Saluja, and V. D. Agrawal, "Scheduling tests of VLSI systems under power constraints," IEEE Trans. VLSI Systems, vol. 5, pp. 175--185, June 1997.
[11]
D. Czysz, G. Mrugalski, J. Rajski, and J. Tyszer, "Low power decompression of test cubes," US patent application, 2006.
[12]
S. Gerstendorfen and H.-J. Wunderlich, "Minimized power consumption for scan-based BIST," Proc. ITC, pp. 77--84, 1999.
[13]
P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, "A test vector inhibiting technique for low energy BIST design," Proc. VTS, pp. 407--412, 1999.
[14]
P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, and H.-J. Wunderlich, "High defect coverage with low-power test sequences in a BIST environment," IEEE Design & Test, pp. 44--52, 2002.
[15]
T.-C. Huang and K.-J. Lee, "A token scan architecture for low power testing," Proc. ITC, pp. 660--669, 2001.
[16]
V. Iyengar and K. Chakrabarty, "Precedence-based, preemptive, and power-constrained test scheduling for system-on-chip," Proc. VTS, pp. 368--374, 2001.
[17]
S. Kajihara, K. Ishida, and K. Miyase, "Test vector modification for power reduction during scan testing," Proc. VTS, pp. 160--165, 2002.
[18]
J. Lee and N. A. Touba, "LFSR-reseeding scheme achieving low-power dissipation during test," IEEE Trans. CAD, vol. 26, pp. 396--401, Feb. 2007.
[19]
J. Lee and N. A. Touba, "Low power test data compression based on LFSR reseeding," Proc. ICCD, pp. 180--185, 2004.
[20]
X. Lin, D. Czysz, M. Kassab, G. Mrugalski, J. Rajski, and J. Tyszer, "Low power scan test application in test compression environment," US patent application, 2007.
[21]
J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, "Embedded deterministic test," IEEE Trans. CAD, vol. 23, pp. 776--792, May 2004.
[22]
S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz, and J. Rajski, "Preferred fill: a scalable method to reduce capture power for scan based designs," Proc. ITC, 2006, paper 32.2.
[23]
P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding," Proc. ICCD, pp. 474--479, 2002.
[24]
R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction technique to control scan vector power dissipation," Proc. VTS, pp. 35--40, 2000.
[25]
R. Sankaralingam, B. Pouya, and N. A. Touba, "Reducing power dissipation during test using scan chain disable," Proc. VTS, pp. 319--324, 2001.
[26]
R. Sankaralingam and N. A. Touba, "Controlling peak power during scan testing," Proc. VTS, pp. 153--159, 2002.
[27]
J. Saxena, K. B. Butler, and L. Whetsel, "An analysis of power reduction techniques in scan testing," Proc. ITC, pp. 670--677, 2001.
[28]
O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, "Test power reduction through minimization of scan chain transitions," Proc. VTS, pp. 166--171, 2002.
[29]
S. Wang, "Generation of low power dissipation and high fault coverage patterns for scan-based BIST," Proc. ITC, pp. 834--843, 2002.
[30]
S. Wang and S. K. Gupta, "ATPG for heat dissipation minimization during test application," IEEE Trans. Computers, vol. 47, pp. 256--262, Feb. 1998.
[31]
S. Wang and S. K. Gupta, "An automatic test pattern generator for minimizing switching activity during scan testing activity," IEEE Trans. CAD, vol. 21, pp. 954--968, Aug. 2002.
[32]
S. Wang and S. K. Gupta, "LT-RTPG: A new test-per-scan BIST TPG for low switching activity," IEEE Trans. CAD, vol. 25, pp. 1565--1574, Aug. 2006.
[33]
X. Wen, Y. Yamashita, S. Kajihara, L. Wang, K. K. Saluja, and K. Kinoshita, "On low-capture-power test generation for scan testing," Proc. VTS, pp. 265--270, 2005.
[34]
X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L. Wang, K. K. Saluja, and K. Kinoshita, "Low-capture-power test generation for scan-based at-speed testing," Proc. ITC, pp. 1--10, 2005.
[35]
L. Whetsel, "Adapting scan architectures for low power operation," Proc. ITC, 2000, pp. 863--872.
[36]
C. Zoellin, H.-J. Wunderlich, N. Maeding, and J. Leenstra, "BIST power reduction using scan-chain disable in the Cell processor," Proc. ITC, 2006, paper 32.3.

Cited By

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  • (2013)High-Quality Statistical Test Compression With Narrow ATE InterfaceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225639432:9(1369-1382)Online publication date: 1-Sep-2013
  • (2012)Test Pattern Generation of Relaxed $n$ -Detect Test SetsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210205620:3(410-423)Online publication date: 1-Mar-2012
  • (2012)Low power test application with selective compaction in VLSI designsProceedings of the 2012 IEEE International Test Conference (ITC)10.1109/TEST.2012.6401532(1-10)Online publication date: 5-Nov-2012
  • Show More Cited By

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      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 04 June 2007

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      Author Tags

      1. VLSI test
      2. compression
      3. low power

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      DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;
      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      Cited By

      View all
      • (2013)High-Quality Statistical Test Compression With Narrow ATE InterfaceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225639432:9(1369-1382)Online publication date: 1-Sep-2013
      • (2012)Test Pattern Generation of Relaxed $n$ -Detect Test SetsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210205620:3(410-423)Online publication date: 1-Mar-2012
      • (2012)Low power test application with selective compaction in VLSI designsProceedings of the 2012 IEEE International Test Conference (ITC)10.1109/TEST.2012.6401532(1-10)Online publication date: 5-Nov-2012
      • (2011)Low power testing - What can commercial DFT tools provide?Proceedings of the 2011 International Green Computing Conference and Workshops10.1109/IGCC.2011.6008609(1-6)Online publication date: 25-Jul-2011
      • (2010)Defect aware X-filling for low-power scan testingProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871138(873-878)Online publication date: 8-Mar-2010
      • (2010)Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test CubesACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011916:1(1-29)Online publication date: 1-Nov-2010
      • (2010)Low-power test in compression-based reconfigurable scan architecturesProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854170(55-60)Online publication date: 6-Sep-2010
      • (2010)On reducing test power and test volume by selective pattern compression schemesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202106118:8(1220-1224)Online publication date: 1-Aug-2010
      • (2010)Self-Freeze Linear Decompressors for Low Power TestingProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.37(63-68)Online publication date: 5-Jul-2010
      • (2009)QC-fillProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874896(1142-1147)Online publication date: 20-Apr-2009
      • Show More Cited By

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