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DOP: a CPU core for teaching basics of computer architecture

Authors:

Milos Becvar,

Alois Pluhacek,

Jiri DanecekAuthors Info & Claims

WCAE '03: Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture

Pages 4 - es

https://doi.org/10.1145/1275521.1275527

Published: 08 June 2003 Publication History

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Abstract

A simple 16-bit processor core called DOP and its teaching environment is presented. The DOP processor illustrates the basic principles of computer organization and is therefore used in the introductory hardware course. Its major features are simplicity, availability of an FPGA implementation and a C compiler. This paper presents the description of the core, HW and SW tools and teaching methodology.

References

[1]

Brorson, M. (2002). MipsIT -- a Simulator and Development Environment using Animation for Computer Architecture Education, In: Proc. of Workshop of Computer Architecture Education, Anchorage, USA

Digital Library

Google Scholar

[2]

Bruschi, S. M. (1999). Simulation as a Tool for Computer Architecture Teaching, In: Proc. of SCS Summer Simulation Conference, pp. 81--86., Orlando, USA

Google Scholar

[3]

Danecek, J., Drápal, F., Pluhácek, A., Salcic, Z., Servit, M. (1994a): DOP -- A Simple Processor for Custom Computing Machines. In: Journal of Microcomputer Applications, vol. 17, pp. 239--253, Academic Press Limited

Digital Library

Google Scholar

[4]

Danecek, J., Drápal, F., Pluhácek, A., Servít, M. (1994b) The Architecture of General-Purpose Processor Cell. In: Proc. of 4th International Workshop on Field-Programmable Logic and Applications, FPL94, pp. 321--325, Prague

Digital Library

Google Scholar

[5]

Danecek, J., Drápal, F., Pluhácek, A., Salcic Z., Servít, M. (1994c) Methodologies for Computer Aided Hardware/Software Co-Design Using Field Programmable Gate Arrays. In: Research Report. Department of Computers, CTU Prague

Google Scholar

[6]

Drápal, F., Danecek, J., Pluhácek, A., Servít, M. (1995), Implementation of a General-Purpose Processor Macro, In: Proc. Design Methodologies for Microelectronics, pp. 89 --97, Smolenice, Slovakia

Google Scholar

[7]

Ellard, D., Holland, D., Murphy, N., Seltzer M. (2002) On the Design of a New CPU Architecture for Pedagogical Purposes In: Proc. of the Workshop of Computer Architecture Education, Anchorage, USA

Digital Library

Google Scholar

[8]

Patterson, D., Hennessy, J. (1998), Computer Organization and Design: The Hardware/Software Interface, 2^nd edition, Morgan Kaufmann Publishers, San Francisco, USA

Digital Library

Google Scholar

[9]

Patterson, D., Hennessy, J. (2002), Computer Architecture A Quantitative Approach, 3rd edition, Morgan Kaufmann Publishers, San Francisco, USA

Digital Library

Google Scholar

[10]

Yurcik, W., Wolffe, G., Holliday, M. (2001). A Survey of Simulators Used in Computer Organization/Architecture Courses, In: Proc. of the 2001 Summer Computer Simulation Conference (SCS 2001), Orlando, USA

Google Scholar

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Sundar STayal V(2021)8-Bit Electromechanical Processor Design for Education in Digital ComputationRecent Advances in Manufacturing, Automation, Design and Energy Technologies10.1007/978-981-16-4222-7_60(533-541)Online publication date: 12-Oct-2021
https://doi.org/10.1007/978-981-16-4222-7_60
Udugama LGeeganage JGehringer E(2006)Students' experimental processorProceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture10.1145/1275620.1275632(7-es)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1145/1275620.1275632

DOP: a CPU core for teaching basics of computer architecture
1. Social and professional topics
  1. Professional topics
    1. Computing education
      1. Computing education programs

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Published In

WCAE '03: Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture

June 2003

108 pages

ISBN:9781450347327

DOI:10.1145/1275521

Conference Chair:
Edward F. Gehringer

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 08 June 2003

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Sundar STayal V(2021)8-Bit Electromechanical Processor Design for Education in Digital ComputationRecent Advances in Manufacturing, Automation, Design and Energy Technologies10.1007/978-981-16-4222-7_60(533-541)Online publication date: 12-Oct-2021
https://doi.org/10.1007/978-981-16-4222-7_60
Udugama LGeeganage JGehringer E(2006)Students' experimental processorProceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture10.1145/1275620.1275632(7-es)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1145/1275620.1275632

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Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Embedded Design Using Programmable Gate Arrays

Technology workshops by in-service teachers for pre-service teachers

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