Article

Clock buffer and wire sizing using sequential programming

Authors:

Matthew R. Guthaus,

Dennis Sylvester,

Richard B. BrownAuthors Info & Claims

DAC '06: Proceedings of the 43rd annual Design Automation Conference

Pages 1041 - 1046

https://doi.org/10.1145/1146909.1147171

Published: 24 July 2006 Publication History

Abstract

This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequential programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the sequential quadratic programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average.

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Cited By

Huang PWang YZhao ZYue D(2024)CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor SizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332859232:1(137-149)Online publication date: Jan-2024
https://doi.org/10.1109/TVLSI.2023.3328592
Ma HHe JLiu YLiu LZhao YJin Y(2021)Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel ProtectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302493840:6(1077-1089)Online publication date: Jun-2021
https://doi.org/10.1109/TCAD.2020.3024938
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889756
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Published In

cover image ACM Conferences

DAC '06: Proceedings of the 43rd annual Design Automation Conference

July 2006

1166 pages

ISBN:1595933816

DOI:10.1145/1146909

General Chair:
Ellen M. Sentovich
Cadence Berkeley Labs, Berkeley, CA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 July 2006

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DAC06: The 43rd Annual Design Automation Conference 2006

July 24 - 28, 2006

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Huang PWang YZhao ZYue D(2024)CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor SizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332859232:1(137-149)Online publication date: Jan-2024
https://doi.org/10.1109/TVLSI.2023.3328592
Ma HHe JLiu YLiu LZhao YJin Y(2021)Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel ProtectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302493840:6(1077-1089)Online publication date: Jun-2021
https://doi.org/10.1109/TCAD.2020.3024938
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889756
Uysal NLiu WEwetz RShibuya T(2019)Latency constraint guided buffer sizing and layer assignment for clock trees with useful skewProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287681(761-766)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287681
Chou CHsiao YChang S(2019)Clock Skew Optimization for Voltage Variation2019 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC.2019.8755674(1-3)Online publication date: Mar-2019
https://doi.org/10.1109/CSTIC.2019.8755674
Farshidi ABehjat LRakai LWestwick D(2017)A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock TreesIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.259858164:4(412-416)Online publication date: Apr-2017
https://doi.org/10.1109/TCSII.2016.2598581
Cho KJang CChong J(2014)Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated CircuitsETRI Journal10.4218/etrij.14.0113.125736:6(931-941)Online publication date: 1-Dec-2014
https://doi.org/10.4218/etrij.14.0113.1257
Farshidi ARakai LBehjat LWestwick DAyala JJones AMadden PCoskun A(2013)A self-tuning multi-objective optimization framework for geometric programming with gate sizing applicationsProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483115(305-310)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483115
Kahng AKang SLee H(2013)Smart non-default routing for clock power reductionProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488846(1-7)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488846
Rakai LFarshidi ABehjat LWestwick DKoh CSze C(2013)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizesProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451956(154-161)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451956
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