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Ferry CYuki TDerrien SRajopadhye S(2023)Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory LayoutIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320149442:5(1546-1559)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3201494
Xu RSha EZhuge QSong YWang H(2023)Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMsJournal of Systems Architecture10.1016/j.sysarc.2022.102799135(102799)Online publication date: Feb-2023
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Index Terms

A data locality optimizing algorithm
1. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Computations on matrices
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

ACM SIGPLAN Notices Volume 26, Issue 6

June 1991

352 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/113446

Editor:
Richard L. Wexelblat
IDA/CSED, Alexandria, VA

Issue’s Table of Contents

PLDI '91: Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
May 1991
356 pages
ISBN:0897914287
DOI:10.1145/113445
Chairman:
David S. Wise
Indiana Univ., Bloomington

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1991

Published in SIGPLAN Volume 26, Issue 6

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Liu HGalindo MXie HWong LShuai HLi YCheng W(2024)Lightweight Deep Learning for Resource-Constrained Environments: A SurveyACM Computing Surveys10.1145/3657282Online publication date: 11-May-2024
https://doi.org/10.1145/3657282
Ferry CYuki TDerrien SRajopadhye S(2023)Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory LayoutIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320149442:5(1546-1559)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3201494
Xu RSha EZhuge QSong YWang H(2023)Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMsJournal of Systems Architecture10.1016/j.sysarc.2022.102799135(102799)Online publication date: Feb-2023
https://doi.org/10.1016/j.sysarc.2022.102799
Gervich LMetelitsa ESteinberg B(2023)Combination of parallelization and skewed tilingProcedia Computer Science10.1016/j.procs.2023.12.024229(228-235)Online publication date: 2023
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