research-article

An efficient phase detector connection structure for the skew synchronization system

Authors:

Hsuan-Ming Chou,

Shih-Chieh ChangAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 729 - 734

https://doi.org/10.1145/1837274.1837457

Published: 13 June 2010 Publication History

Abstract

Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in the skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers have emphasized on ADB placement issues. In this paper, we show that the connection between FFs and PDs can also greatly influence the final clock skew due to the insertion of the PDs. We first analyze the influence of PD connection structures. Then we propose an algorithm to generate a PD connection structure which achieves the minimum influence to the clock skew. Our experimental results are very encouraging.

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Cited By

Chatterjee SChauhan YAmrouch H(2023)Programmable Delay Element Using Dual-Port FeFET for Post-Silicon Clock TuningIEEE Electron Device Letters10.1109/LED.2023.331731644:11(1907-1910)Online publication date: Nov-2023
https://doi.org/10.1109/LED.2023.3317316
Kao MTsai KChang S(2015)A Fault Detection and Tolerance Architecture for Post-Silicon Skew TuningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.233766123:7(1210-1220)Online publication date: Jul-2015
https://doi.org/10.1109/TVLSI.2014.2337661
Murooka DZhang YDong QNakatake S(2015)Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning2015 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2015.91(167-171)Online publication date: Jul-2015
https://doi.org/10.1109/ISVLSI.2015.91
Show More Cited By

Index Terms

An efficient phase detector connection structure for the skew synchronization system
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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Novatek Microelectronics Corp.

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DAC '10

Sponsor:

EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,264 of 4,035 submissions, 31%

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62nd ACM/IEEE Design Automation Conference

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Citations

Cited By

Chatterjee SChauhan YAmrouch H(2023)Programmable Delay Element Using Dual-Port FeFET for Post-Silicon Clock TuningIEEE Electron Device Letters10.1109/LED.2023.331731644:11(1907-1910)Online publication date: Nov-2023
https://doi.org/10.1109/LED.2023.3317316
Kao MTsai KChang S(2015)A Fault Detection and Tolerance Architecture for Post-Silicon Skew TuningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.233766123:7(1210-1220)Online publication date: Jul-2015
https://doi.org/10.1109/TVLSI.2014.2337661
Murooka DZhang YDong QNakatake S(2015)Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning2015 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2015.91(167-171)Online publication date: Jul-2015
https://doi.org/10.1109/ISVLSI.2015.91
Kao MTsai KChou HChang S(2012)Post silicon skew tuning: Survey and analysis17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6165036(646-651)Online publication date: Jan-2012
https://doi.org/10.1109/ASPDAC.2012.6165036
Kao MTsai KChang SPhillips JHu AGraeb H(2011)A robust architecture for post-silicon skew tuningProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132493(774-778)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132493
Lung CSu YHuang SShi YChang SStok LDutt NHassoun S(2011)Fault-tolerant 3D clock networkProceedings of the 48th Design Automation Conference10.1145/2024724.2024872(645-651)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024872
Kao MTsai KChang S(2011)A robust architecture for post-silicon skew tuningProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105417(774-778)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105417

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