Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/1787275.1787333acmconferencesArticle/Chapter ViewAbstractPublication PagescfConference Proceedingsconference-collections
research-article

Reversible online BIST using bidirectional BILBO

Published: 17 May 2010 Publication History

Abstract

Test generation for reversible circuits is currently gaining interest due to its feasibility towards quantum implementation and asymptotically zero-power dissipation. A novel BIST (Built-In-Self-Test) method for reversible circuits is proposed in this paper. New bidirectional D-latch and D-flipflop designs are introduced. A Reversible BILBO (Built-in-Logic-Block-Observer) based on conventional BILBO is designed to facilitate the BIST procedure. The complete test procedure is executed and experimental results are analyzed for both stuck at and missing gate faults (MGF) with 100% fault coverage.

References

[1]
Landauer, R. 1961. Irreversibility and heat generation in the computing process, IBM J. Research and Development, vol.3, 183--191.
[2]
Bennett, C. H., 1973. Logical reversibility of computation," IBM J. Research and Development, 525--532, November.
[3]
Frank, M. P. 2005. Introduction to reversible computing: motivation, progress, and challenges, Proc. ACM Computing Frontiers (CF'05), pp. 385--390.
[4]
Fredkin, E., and Toffoli, T. 1982. Conservative logic, Journal of Theoretical Physics, vol. 21, 219--253.
[5]
Sasao, T., and Kinoshita, K. 1979. Conservative logic elements and their universality, IEEE Trans. Comput., vol. C-28, no. 9, 682--685.
[6]
Bushnell, M., and Agrawal, V., 2000. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Kluwer Academic Publishers.
[7]
Shende, V., Prasad, A., Markov, I., and Hayes, J. P. 2003. Synthesis of Reversible Logic Circuits. IEEE Trans. CAD of Intergrated Circuits and Systems, Vol.22, No. 6, 710--722.
[8]
Maslov, D., Dueck, G., and Miller, D. M. 2005. Toffoli Network Synthesis with Templates, IEEE Trans. CAD of Integrated Circuits and Systems. Vol.24, No.6, June 2005, pp.807--817.
[9]
Desoete, B., and De Vos, A. 2002. A reversible carry-look-ahead adder using control gates, in Integration, the V.L.S.I. Journal, volume 33 (2002) 89--104.
[10]
Patel, K. N., Hayes J. P., and Markov, I. L. 2003. Fault Testing for Reversible Circuits, the VLSI Test Symposium, Napa, CA (April 2003).
[11]
Perkowski, M., Biamonte, J., and Lukac, M. 2005. Test Generation and Fault Localization for Quantum Circuits, Multiple-Valued Logic, IEEE International Symposium on, pp. 62--68, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).
[12]
Polian, I., Fiehn, T., Becker, B., Hayes, J. P. 2005. A Family of Logical Fault Models for Reversible Circuits, ats, pp.422--427, 14th Asian Test Symposium (ATS'05).
[13]
Wille, R., Grosse, D., Frehse, S., Dueck, G. W., and Drechsler, R. 2009. Debugging of Toffoli Networks, Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE'09. 20-24 April 2009 Page(s):1284--1289.
[14]
Wille, R., and Drechsler, R. 2009. BDD-based synthesis of reversible logic for large functions, Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE, vol., no., pp.270--275, 26--31.
[15]
Steininger, A. 2000. Testing and built-in self-test - A survey, Journal of Systems Architecture, Volume 46, Issue 9, July 2000, Pages 721--747.
[16]
Steane, A. M. 2004. How to build a 300 bit, 1 gop quantum computer, quantph/0412165.
[17]
Hayes, J. P., Polian, I., and Becker, B. 2004. Testing for Missing-Gate Faults in Reversible Circuits. In Proceedings of the 13th Asian Test Symposium (November 15 - 17, 2004). ATS. IEEE Computer Society, Washington, DC, 100--105.
[18]
Rahaman, H., Kole, D. K., Das, D. K., and Bhattacharya, B. B. 2008. On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. In Proceedings of the 21st international Conference on VLSI Design (January 04 - 08, 2008). VLSID. IEEE Computer Society, Washington, DC, 163--168.
[19]
Polian, I., Fiehn, T., Becker, B., Hayes, J. P, 2005. A Family of Logical Fault Models for Reversible Circuits, Asian Test Symposium, pp. 422--427, 14th Asian Test Symposium (ATS'05).
[20]
Maslov, D., Dueck, G., and Scott, N. 2004. Reversible Logic Synthesis Benchmarks Page. http://www.cs.uvic.ca/~dmaslov/, http://webhome.cs.uvic.ca/~dmaslov/
[21]
Mondron, L., 2003. Bidirectional flip-flop, US Patent 6590349.
[22]
Vasudevan, D. P., Lala, P. K., Di, J., and Parkerson, J. P. 2006. Reversible-LogicDesign With Online Testability, IEEE Transactions on Instrumentation and Measurement, VOL. 55, NO. 2, 406--414.

Cited By

View all
  • (2018)Low Power Testable Reversible Combinational Circuits2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS)10.1109/ICCONS.2018.8663240(1485-1489)Online publication date: Jun-2018
  • (2015)Implementation of Reversible Arithmetic and Logical Unit and Its BILBO TestingMicroelectronics, Electromagnetics and Telecommunications10.1007/978-81-322-2728-1_57(601-613)Online publication date: 25-Dec-2015
  • (2012)Testing of Reversible Combinational CircuitsAdvances in Communication, Network, and Computing10.1007/978-3-642-35615-5_7(46-53)Online publication date: 2012

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
CF '10: Proceedings of the 7th ACM international conference on Computing frontiers
May 2010
370 pages
ISBN:9781450300445
DOI:10.1145/1787275
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 May 2010

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. bilbo
  2. bist
  3. reversible logic
  4. testing

Qualifiers

  • Research-article

Conference

CF'10
Sponsor:
CF'10: Computing Frontiers Conference
May 17 - 19, 2010
Bertinoro, Italy

Acceptance Rates

CF '10 Paper Acceptance Rate 30 of 113 submissions, 27%;
Overall Acceptance Rate 273 of 785 submissions, 35%

Upcoming Conference

CF '25

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 17 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2018)Low Power Testable Reversible Combinational Circuits2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS)10.1109/ICCONS.2018.8663240(1485-1489)Online publication date: Jun-2018
  • (2015)Implementation of Reversible Arithmetic and Logical Unit and Its BILBO TestingMicroelectronics, Electromagnetics and Telecommunications10.1007/978-81-322-2728-1_57(601-613)Online publication date: 25-Dec-2015
  • (2012)Testing of Reversible Combinational CircuitsAdvances in Communication, Network, and Computing10.1007/978-3-642-35615-5_7(46-53)Online publication date: 2012

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media