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Modular code generation from synchronous block diagrams: modularity vs. code size

Published: 21 January 2009 Publication History

Abstract

We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composite block independently from context (i.e., without knowing in which diagrams the block is to be used) and using minimal information about the internals of the block. In previous work, we have shown how modular code can be generated by computing a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. We have also introduced a quantified notion of modularity in terms of the number of interface functions generated per block, and showed how to minimize this number, which is essential for scalability. Finally, we have exposed the fundamental trade-off between modularity and reusability (set of diagrams the block can be used in).
In this paper we explore another trade-off: modularity vs. code size. We show that our previous technique, although it achieves maximal reusability and is optimal in terms of modularity, may result in code replication and therefore large code sizes, something often unacceptable in an embedded system context. We propose to remedy this by generating code with no replication, and show that this generally results in some loss of modularity. We show that optimizing modularity while maintaining maximal reusability and zero replication is an intractable problem (NP-complete). We also show that this problem can be solved using a simple iterative procedure that checks satisfiability of a sequence of propositional formulas. We report on a new prototype implementation and experimental results. The latter demonstrate the practical interest in our methods.

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  • (2019)Blech, Imperative Synchronous Programming!Languages, Design Methods, and Tools for Electronic System Design10.1007/978-3-030-31585-6_9(161-186)Online publication date: 21-Dec-2019
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Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 44, Issue 1
POPL '09
January 2009
453 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1594834
Issue’s Table of Contents
  • cover image ACM Conferences
    POPL '09: Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
    January 2009
    464 pages
    ISBN:9781605583792
    DOI:10.1145/1480881
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2009
Published in SIGPLAN Volume 44, Issue 1

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Author Tags

  1. block diagrams
  2. clustering
  3. code generation
  4. embedded software
  5. np-complete
  6. synchronous languages

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Cited By

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  • (2024)Automated level-based clustering of dataflow actors for controlled scheduling complexityJournal of Systems Architecture10.1016/j.sysarc.2024.103217154(103217)Online publication date: Sep-2024
  • (2019)Optimization techniques for time-critical cyber-physical systemsProceedings of the Workshop on Design Automation for CPS and IoT10.1145/3313151.3313168(41-50)Online publication date: 15-Apr-2019
  • (2019)Blech, Imperative Synchronous Programming!Languages, Design Methods, and Tools for Electronic System Design10.1007/978-3-030-31585-6_9(161-186)Online publication date: 21-Dec-2019
  • (2018)Blech, Imperative Synchronous Programming!2018 Forum on Specification & Design Languages (FDL)10.1109/FDL.2018.8524036(5-16)Online publication date: Sep-2018
  • (2017)Performance evaluation of MATLAB/Simulink models for fitting embedded multicore systems2017 25th International Conference on Software, Telecommunications and Computer Networks (SoftCOM)10.23919/SOFTCOM.2017.8115559(1-6)Online publication date: Sep-2017
  • (2017)A formally verified compiler for LustreACM SIGPLAN Notices10.1145/3140587.306235852:6(586-601)Online publication date: 14-Jun-2017
  • (2017)A formally verified compiler for LustreProceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3062341.3062358(586-601)Online publication date: 14-Jun-2017
  • (2017)Automatic paral ellizati on of Simulink models for multicore embedded systems development2017 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC)10.1109/IINTEC.2017.8325924(118-123)Online publication date: Oct-2017
  • (2016)Automatic Parallelization of Multirate Block Diagrams of Control Systems on Multicore PlatformsACM Transactions on Embedded Computing Systems10.1145/295005516:1(1-26)Online publication date: 13-Oct-2016
  • (2016)In-Place Update in a Dataflow Synchronous LanguageProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906379(40-49)Online publication date: 23-May-2016
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