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Deconstructing new cache designs for thwarting software cache-based side channel attacks

Published: 31 October 2008 Publication History

Abstract

Software cache-based side channel attacks present a serious tthreat to computer systems. Previously proposed countermeasures were either too costly for practical use or only effective against particular attacks. Thus, a recent work identified cache interferences in general as the root cause and proposed two new cache designs, namely partition-locked cache (PLcache) and random permutation cache(RPcache), to defeat cache-based side channel attacks by eliminating/obfuscating cache interferences. In this paper, we analyze these new cache designs and identify significant vulnerabilities and shortcomings of those new cache designs. We also propose possible solutions and improvements over the original new cache designs to overcome the identified shortcomings.

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Cited By

View all
  • (2024)SecurityCloak: Protection against cache timing and speculative memory access attacksJournal of Systems Architecture10.1016/j.sysarc.2024.103107150(103107)Online publication date: May-2024
  • (2023)SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-VACM Transactions on Architecture and Code Optimization10.1145/356605320:1(1-26)Online publication date: 10-Feb-2023
  • (2023)Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks2023 Silicon Valley Cybersecurity Conference (SVCC)10.1109/SVCC56964.2023.10165527(1-8)Online publication date: 17-May-2023
  • Show More Cited By

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cover image ACM Conferences
CSAW '08: Proceedings of the 2nd ACM workshop on Computer security architectures
October 2008
72 pages
ISBN:9781605583006
DOI:10.1145/1456508
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 31 October 2008

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Author Tags

  1. cache architecture
  2. cache attack
  3. cryptanalysis
  4. microarchitectural analysis
  5. side-channel analysis
  6. timing attack

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Cited By

View all
  • (2024)SecurityCloak: Protection against cache timing and speculative memory access attacksJournal of Systems Architecture10.1016/j.sysarc.2024.103107150(103107)Online publication date: May-2024
  • (2023)SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-VACM Transactions on Architecture and Code Optimization10.1145/356605320:1(1-26)Online publication date: 10-Feb-2023
  • (2023)Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks2023 Silicon Valley Cybersecurity Conference (SVCC)10.1109/SVCC56964.2023.10165527(1-8)Online publication date: 17-May-2023
  • (2023)Guard Cache: Creating Noisy Side-ChannelsIEEE Computer Architecture Letters10.1109/LCA.2023.328971022:2(97-100)Online publication date: Jul-2023
  • (2022)Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their TracksACM Transactions on Architecture and Code Optimization10.1145/356369520:1(1-24)Online publication date: 17-Nov-2022
  • (2022)Imitating Functional Operations for Mitigating Side-Channel LeakageIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307024341:4(868-881)Online publication date: Apr-2022
  • (2022)Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED)10.1109/SEED55351.2022.00023(179-189)Online publication date: Sep-2022
  • (2021)Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It2021 IEEE Symposium on Security and Privacy (SP)10.1109/SP40001.2021.00050(955-969)Online publication date: May-2021
  • (2021)A Survey on Cache Timing Channel Attacks for Multicore ProcessorsJournal of Hardware and Systems Security10.1007/s41635-021-00115-35:2(169-189)Online publication date: 19-May-2021
  • (2021)A Formal Analysis of Prefetching in Profiled Cache-Timing Attacks on Block CiphersJournal of Cryptology10.1007/s00145-021-09394-z34:3Online publication date: 20-May-2021
  • Show More Cited By

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