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Prefetch unit for vector operations on scalar computers

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Ivan SklenářAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 20, Issue 4

Pages 31 - 37

https://doi.org/10.1145/142880.142891

Published: 01 September 1992 Publication History

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Abstract

Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps trace of the history of memory references, and therefore initializes rarely any superfluous prefetches.

References

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[2] Fu, J. W. C., Patel, J. H., Data prefetching in multiprocessor vector cache memories, Proc. 18th. ISCA, Comp. Architecture News, 19 (1991) 2, 54-63.

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[3] Hockney, R.W., Jesshoppe, C.R., Parallel computers, Adam Hilger Ltd., Bristol, 1982.

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[4] Johnson, E. E., Working set prefetching for cache memories, Computer Architecture News, 17, [6] (Dec. 1989) 137-141.

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Cited By

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Jia LMcmahon JGudaparthi SSingh SBalasubramonian RTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)PATHFINDER: Practical Real-Time Learning for Data PrefetchingProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651332(785-800)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651332
Lee YKim S(2016)CLAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.248828224:5(1770-1782)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2488282
Michaud P(2016)Best-offset hardware prefetching2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446087(469-480)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446087
Show More Cited By

Index Terms

Prefetch unit for vector operations on scalar computers
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Systolic arrays
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Prefetch unit for vector operations on scalar computers (abstract)
Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecutre and ...
Prefetch unit for vector operations on scalar computers (abstract)
ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecutre and ...

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 1992

Published in SIGARCH Volume 20, Issue 4

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Cited By

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Jia LMcmahon JGudaparthi SSingh SBalasubramonian RTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)PATHFINDER: Practical Real-Time Learning for Data PrefetchingProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651332(785-800)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651332
Lee YKim S(2016)CLAPIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.248828224:5(1770-1782)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2488282
Michaud P(2016)Best-offset hardware prefetching2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446087(469-480)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446087
NATARAJAN RMEKKAT VHSU WZHAI A(2012)EFFECTIVENESS OF COMPILER-DIRECTED PREFETCHING ON DATA MINING BENCHMARKSJournal of Circuits, Systems and Computers10.1142/S021812661240006321:02(1240006)Online publication date: Apr-2012
https://doi.org/10.1142/S0218126612400063
McKee SWulf WLandon T(2005)Bounds on memory bandwidth in streamed computationsEURO-PAR '95 Parallel Processing10.1007/BFb0020457(83-99)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0020457
Phalke VGopinath B(2005)A miss history-based architecture for cache prefetchingMemory Management10.1007/3-540-60368-9_35(381-398)Online publication date: 1-Jun-2005
https://doi.org/10.1007/3-540-60368-9_35
Zhang CMcKee SReynders JVeidenbaum A(2000)Hardware-only stream prefetching and dynamic access orderingProceedings of the 14th international conference on Supercomputing10.1145/335231.335247(167-175)Online publication date: 8-May-2000
https://dl.acm.org/doi/10.1145/335231.335247
Koppelman D(2000)Neighborhood prefetching on multiprocessors using instruction historyProceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)10.1109/PACT.2000.888337(123-132)Online publication date: 2000
https://doi.org/10.1109/PACT.2000.888337
Zucker DLee RFlynn M(2000)Hardware and software cache prefetching techniques for MPEG benchmarksIEEE Transactions on Circuits and Systems for Video Technology10.1109/76.85645510:5(782-796)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1109/76.856455
McKee SWulf WAylor JSalinas MKlenke RHong SWeikle D(2000)Dynamic Access Ordering for Streamed ComputationsIEEE Transactions on Computers10.1109/12.89594149:11(1255-1271)Online publication date: 1-Nov-2000
https://dl.acm.org/doi/10.1109/12.895941
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Abstract

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