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Source-level timing annotation and simulation for a heterogeneous multiprocessor

Published: 10 March 2008 Publication History

Abstract

A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing accuracy. This simulator is API-compatible with the multiprocessor's operating system. Therefore, it can compile and run unmodified applications on the host PC. This flow has been implemented for MuSIC (Multiple SIMD Cores) [6], a heterogeneous multiprocessor developed at Infineon to support Software Defined Radio (SDR). When compared with an optimized cycle-accurate VP of MuSIC on a variety of tests, including a multiprocessor JPEG encoder, the accuracy is within 20%, with speedups from 10x to 1000x.

References

[1]
Open SystemC Initiative Web Site: http://www.systemc.org.
[2]
Uncrustify web site: http://uncrustify.sourceforge.net/.
[3]
VaST Website: http://www.vastsystems.com.
[4]
F. Balarin, et. al. Hardware-software co-design of embedded systems: the Polis approach. Kluwer Academic Publishers, Boston; Dordrecht, 1997.
[5]
J. Bammi, et. al. Software performance estimation strategies in a system-level design tool. Proc. of CODES, pages 82--6, 2000.
[6]
H. -M. Bluethgen, et. al. A programmable baseband platform for software-defined radio. In Proceedings of SDR FORUM, 2004.
[7]
M. Guthaus, et. al. Mibench: A free, commercially representative embedded benchmark suite. Proc. of the 4th Workshop on Workload Characterization, pages 3--14, 2001.
[8]
J. M. Paul, et. al. High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Des. Autom. Electron. Syst., 10(3):431--461, 2005.
[9]
K. Suzuki and A. Sangiovanni-Vincentelli. Efficient software performance estimation methods for hardware/software codesign. Proceedings of the DAC, pages 605--610, 1996.
[10]
L. -C. Wu. Interactive Source-Level Debugging of Optimized Code. PhD thesis, University of Illinois at Urbana-Champaign, August 1999.

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cover image ACM Conferences
DATE '08: Proceedings of the conference on Design, automation and test in Europe
March 2008
1575 pages
ISBN:9783981080131
DOI:10.1145/1403375
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 March 2008

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DATE '08
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  • The Russian Academy of Sciences
DATE '08: Design, Automation and Test in Europe
March 10 - 14, 2008
Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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  • (2020)GeoSim 2019 workshop report: The 2nd ACM SIGSPATIAL International Workshop on Geospatial SimulationSIGSPATIAL Special10.1145/3383653.338366111:3(20-22)Online publication date: 13-Feb-2020
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