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Background memory area estimation for multidimensional signal processing systems

Published: 01 June 1995 Publication History

Abstract

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity.< >

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  • (2010)On minimizing register usage of linearly scheduled algorithms with uniform dependenciesComputer Languages, Systems and Structures10.1016/j.cl.2009.12.00136:3(250-267)Online publication date: 1-Oct-2010
  • (2008)Computation of the minimum data storage and applications in memory management for multimedia signal processingIntegrated Computer-Aided Engineering10.5555/1367166.136717215:2(181-196)Online publication date: 1-Apr-2008
  • (2008)Dynamic memory access management for high-performance DSP applications using high-level synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200082116:11(1454-1464)Online publication date: 1-Nov-2008
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  1. Background memory area estimation for multidimensional signal processing systems

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        cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
        IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 3, Issue 2
        June 1995
        188 pages
        ISSN:1063-8210
        Issue’s Table of Contents

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        IEEE Educational Activities Department

        United States

        Publication History

        Published: 01 June 1995

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        View all
        • (2010)On minimizing register usage of linearly scheduled algorithms with uniform dependenciesComputer Languages, Systems and Structures10.1016/j.cl.2009.12.00136:3(250-267)Online publication date: 1-Oct-2010
        • (2008)Computation of the minimum data storage and applications in memory management for multimedia signal processingIntegrated Computer-Aided Engineering10.5555/1367166.136717215:2(181-196)Online publication date: 1-Apr-2008
        • (2008)Dynamic memory access management for high-performance DSP applications using high-level synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200082116:11(1454-1464)Online publication date: 1-Nov-2008
        • (2008)Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing ApplicationsJournal of Signal Processing Systems10.1007/s11265-008-0244-053:1-2(51-71)Online publication date: 1-Nov-2008
        • (2008)Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing ApplicationsJournal of Signal Processing Systems10.1007/s11265-008-0178-653:3(301-321)Online publication date: 1-Dec-2008
        • (2007)Fast memory footprint estimation based on maximal dependency vector calculationProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266447(379-384)Online publication date: 16-Apr-2007
        • (2007)Incremental hierarchical memory size estimation for steering of loop transformationsACM Transactions on Design Automation of Electronic Systems10.1145/1278349.127836312:4(50-es)Online publication date: 1-Sep-2007
        • (2007)Computation of storage requirements for multi-dimensional signal processing applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89524615:4(447-460)Online publication date: 1-Apr-2007
        • (2007)Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoCDesign Automation for Embedded Systems10.1007/s10617-007-9009-411:4(249-283)Online publication date: 1-Dec-2007
        • (2006)Buffer memory optimization for video codec application modeled in SimulinkProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147084(689-694)Online publication date: 24-Jul-2006
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