research-article

Designing Circuits with Partial Scan

Authors:

Vishiwani D. Agrawal,

Kwang-Ting Cheng,

Daniel D. Johnson,

Tony Sheng LinAuthors Info & Claims

IEEE Design & Test, Volume 5, Issue 2

Pages 8 - 15

https://doi.org/10.1109/54.2032

Published: 01 March 1988 Publication History

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Abstract

In this scan design methodology, only selected faults are targeted for detection. These faults are those not detected by the designer's functional vectors. The test generator decides exactly which flip-flops should be scanned using one of two methods. In the first method, all possible tests are generated for each target fault, and the set of tests requiring the fewest flip-flops is selected. In the second method, only one test is generated for each fault, and the use of flip-flops is avoided as much as possible during test generation. Examples of actual VLSI circuits show a savings of at least a 40% in full-scan overhead.

References

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3. M.R. Mercer, V.D. Agrawal, and C.M. Roman, "Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation," Proc. Int'l Test Conf., Oct. 1981, pp. 561-565.

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4. E. Trischler, "Incomplete Scan Path with an Automatic Test Generation Methodology," Proc. Int'l Test Conf., Nov. 1980, pp. 153-162.

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Cited By

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Sinanoglu OAgrawal V(2013)Eliminating the Timing Penalty of ScanJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5352-529:1(103-114)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1007/s10836-013-5352-5
Krug MMoraes MLubaszewski MCoelho CJacobi RBecker J(2006)Using a software testing technique to identify registers for partial scan implementationProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150396(208-213)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150396
Aksenova G(2004)Optimization of Parallel-Series Self-Testing for Discrete DevicesAutomation and Remote Control10.1023/B:AURC.0000038732.75638.3d65:8(1312-1327)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1023/B%3AAURC.0000038732.75638.3d
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Designing Circuits with Partial Scan

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The path delay fault testability of sequential circuits is limited by state transitions that can be produced during normal operation. As a result, there may be untestable faults some of which may affect circuit behavior. The authors first extend the ...

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Published In

IEEE Design & Test Volume 5, Issue 2

March 1988

52 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 March 1988

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Sinanoglu OAgrawal V(2013)Eliminating the Timing Penalty of ScanJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5352-529:1(103-114)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1007/s10836-013-5352-5
Krug MMoraes MLubaszewski MCoelho CJacobi RBecker J(2006)Using a software testing technique to identify registers for partial scan implementationProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150396(208-213)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150396
Aksenova G(2004)Optimization of Parallel-Series Self-Testing for Discrete DevicesAutomation and Remote Control10.1023/B:AURC.0000038732.75638.3d65:8(1312-1327)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1023/B%3AAURC.0000038732.75638.3d
Greene BMourad S(2002)Partial Scan Testing on the Register-Transfer LevelJournal of Electronic Testing: Theory and Applications10.1023/A:102080112331118:6(613-626)Online publication date: 1-Dec-2002
https://dl.acm.org/doi/10.1023/A%3A1020801123311
Lin XPomeranz IReddy S(1999)Full scan fault coverage with partial scanProceedings of the conference on Design, automation and test in Europe10.1145/307418.307545(97-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307545
Makar S(1998)A layout-based approach for ordering scan chain flip-flopsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745613(341-347)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745613
Flottes MPires RRouzeyre BVolpe LDewilde PRammig FMusgrave G(1998)Scanning datapathsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368462(921-922)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368462
Nachman LSaluja KUpadhyaya SReuse R(1998)A Novel Approach to Random Pattern Testing of Sequential CircuitsIEEE Transactions on Computers10.1109/12.65609747:1(129-134)Online publication date: 1-Jan-1998
https://dl.acm.org/doi/10.1109/12.656097
Chen CHwang T(1998)Layout Driven Selection and Chaining of Partial Scan Flip-FlopsJournal of Electronic Testing: Theory and Applications10.1023/A:100838101552713:1(19-27)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1023/A%3A1008381015527
Abadir MKapur R(1997)Cost-Driven Ranking of Memory Elements for Partial IntrusionIEEE Design & Test10.1109/54.60599414:3(45-50)Online publication date: 1-Jul-1997
https://dl.acm.org/doi/10.1109/54.605994
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A partial scan methodology for testing self-timed circuits

Designing new ternary reversible subtractor circuits

Synthesis of delay verifiable sequential circuits using partial enhanced scan

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