research-article

A realistic fault model and test algorithms for static random access memories

Authors:

R. Dekker,

F. Beenker,

L. ThijssenAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 9, Issue 6

Pages 567 - 572

https://doi.org/10.1109/43.55188

Published: 01 November 2006 Publication History

Abstract

Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses

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Lee HLee SKang S(2023)RA-Aware Fail Data Collection Architecture for Cost ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.334336932:6(1136-1149)Online publication date: 21-Dec-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3343369
Maddela VSinha SParvathi MSharma V(2023)Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron TechnologyWireless Personal Communications: An International Journal10.1007/s11277-023-10704-w132:3(2123-2141)Online publication date: 28-Aug-2023
https://dl.acm.org/doi/10.1007/s11277-023-10704-w
Siddiqui IQureshi NShaikh MChowdhry BAbbas ABashir ALee S(2019)Stuck-at Fault Analytics of IoT Devices Using Knowledge-based Data Processing Strategy in Smart GridWireless Personal Communications: An International Journal10.1007/s11277-018-5739-9106:4(1969-1983)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s11277-018-5739-9
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A realistic fault model and test algorithms for static random access memories
1. Computer systems organization
2. Hardware
  1. Integrated circuits

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 9, Issue 6

November 2006

109 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Lee HLee SKang S(2023)RA-Aware Fail Data Collection Architecture for Cost ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.334336932:6(1136-1149)Online publication date: 21-Dec-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3343369
Maddela VSinha SParvathi MSharma V(2023)Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron TechnologyWireless Personal Communications: An International Journal10.1007/s11277-023-10704-w132:3(2123-2141)Online publication date: 28-Aug-2023
https://dl.acm.org/doi/10.1007/s11277-023-10704-w
Siddiqui IQureshi NShaikh MChowdhry BAbbas ABashir ALee S(2019)Stuck-at Fault Analytics of IoT Devices Using Knowledge-based Data Processing Strategy in Smart GridWireless Personal Communications: An International Journal10.1007/s11277-018-5739-9106:4(1969-1983)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s11277-018-5739-9
Leduc-Primeau FGripon VRabbat MGross W(2016)Fault-Tolerant Associative Memories Based on $c$-Partite GraphsIEEE Transactions on Signal Processing10.1109/TSP.2015.248960064:4(829-841)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TSP.2015.2489600
Li JTseng THou C(2010)Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202236318:9(1361-1366)Online publication date: 1-Sep-2010
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Li JHuang C(2007)An Efficient Diagnosis Scheme for RAMs with Simple Functional FaultsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.12.2703E90-A:12(2703-2711)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1093/ietfec/e90-a.12.2703
Benso ABosio ACarlo SNatale GPrinetto PGielen G(2006)Automatic march tests generations for static linked faults in SRAMsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131830(1258-1263)Online publication date: 6-Mar-2006
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Li JTang T(2005)Testing comparison faults of ternary CAMs based on comparison faults of binary CAMsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120745(65-70)Online publication date: 18-Jan-2005
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Li JTseng TWey C(2005)An Efficient Transparent Test Scheme for Embedded Word-Oriented MemoriesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.56(574-579)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.56
Bhadra JMartin AAbraham J(2005)A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessorFormal Methods in System Design10.1007/s10703-005-2250-127:1-2(67-112)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1007/s10703-005-2250-1
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