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Optimal aspect ratios of building blocks in VLSI

Published: 01 November 2006 Publication History

Abstract

The building blocks in a given floorplan have several possible physical implementations yielding different layouts. A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimized. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. The high efficiency of the algorithm stems from the branching strategy and the bounding function used in the search procedure. The branch-and-bound algorithm is supplemented by a heuristic minimization procedure which further prunes the search, is computationally efficient, and does not prevent achieving a global minimum. Finally, the authors show how the nonslicing and the slicing algorithms can be combined to handle efficiently very large general floorplans

Cited By

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  • (2003)Floorplanning of pipelined array modules using sequence pairsProceedings of the 2003 international symposium on Physical design10.1145/640000.640032(143-150)Online publication date: 6-Apr-2003
  • (2002)Monotone bipartitioning problem in a planar point set with applications to VLSIACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445377:2(231-248)Online publication date: 1-Apr-2002
  • (2001)Slicible rectangular graphs and their optimal floorplansACM Transactions on Design Automation of Electronic Systems10.1145/502175.5021766:4(447-470)Online publication date: 1-Oct-2001
  • Show More Cited By

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 8, Issue 2
November 2006
89 pages

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IEEE Press

Publication History

Published: 01 November 2006

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Cited By

View all
  • (2003)Floorplanning of pipelined array modules using sequence pairsProceedings of the 2003 international symposium on Physical design10.1145/640000.640032(143-150)Online publication date: 6-Apr-2003
  • (2002)Monotone bipartitioning problem in a planar point set with applications to VLSIACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445377:2(231-248)Online publication date: 1-Apr-2002
  • (2001)Slicible rectangular graphs and their optimal floorplansACM Transactions on Design Automation of Electronic Systems10.1145/502175.5021766:4(447-470)Online publication date: 1-Oct-2001
  • (2000)Classical floorplanning harmful?Proceedings of the 2000 international symposium on Physical design10.1145/332357.332401(207-213)Online publication date: 1-May-2000
  • (2000)Incremental physical designProceedings of the 2000 international symposium on Physical design10.1145/332357.332379(84-92)Online publication date: 1-May-2000
  • (2000)Incorporating Yield Enhancement into the Floorplanning ProcessIEEE Transactions on Computers10.1109/12.86221349:6(532-541)Online publication date: 1-Jun-2000
  • (1996)Geometric bipartitioning problem and its applications to VLSIProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834715Online publication date: 3-Jan-1996
  • (1996)Area minimization for hierarchical floorplansAlgorithmica10.1007/BF0194088115:6(550-571)Online publication date: 1-Jun-1996
  • (1995)An optimal algorithm for area minimization of slicing floorplansProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225096(480-484)Online publication date: 1-Dec-1995
  • (1994)Area minimization for hierarchical floorplansProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191509(436-440)Online publication date: 6-Nov-1994
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