Cited By
View all- Drach NSeznec AWolfe AMangione-Smith W(1993)MIDEEProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255286(193-201)Online publication date: 1-Dec-1993
Reducing Branch Delay to Zero in Pipelined Processors
Abstract
A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.
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- Reducing Branch Delay to Zero in Pipelined Processors
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Published: 01 March 1993
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View all- Drach NSeznec AWolfe AMangione-Smith W(1993)MIDEEProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255286(193-201)Online publication date: 1-Dec-1993