research-article

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems

Authors:

Chun Jason Xue,

Qingfeng Zhuge,

Edwin H.-M ShaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 23, Issue 4

Pages 654 - 663

https://doi.org/10.1109/TVLSI.2014.2321571

Published: 01 April 2015 Publication History

Abstract

Phase change memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics, such as low-cost, shock-resistivity, nonvolatility, high density, and low leakage power. However, relatively low endurance has limited its practical applications. In this paper, in addition to existing hardware level optimizations, we propose software enabled wear-leveling techniques to further extend PCMs lifetime when it is adopted in embedded systems. Most existing software optimization techniques focus on reducing the total number of writes to PCM, but none of them consider wear leveling, in which the writes are distributed more evenly over the PCM. An integer linear programming formulation and a polynomial-time algorithm, the software wear-leveling algorithm, are proposed in this paper to achieve wear leveling without hardware overhead. According to the experimental results, the proposed techniques can reduce the number of writes on the most-written addresses by more than 80% when compared with a greedy algorithm, and by more than 60% when compared with the existing optimal data allocation algorithm with under 6% memory access overhead.

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 23, Issue 4

April 2015

192 pages

ISSN:1063-8210

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Copyright © 2014.

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IEEE Educational Activities Department

United States

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Published: 01 April 2015

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https://dl.acm.org/doi/10.1109/TC.2024.3404064
Du YHuang SZhou YLi Q(2023)Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error CharacteristicsACM Transactions on Design Automation of Electronic Systems10.1145/358507528:3(1-25)Online publication date: 18-Apr-2023
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Oh DMoon YHam DHam TPark YLee JAhn JLee E(2022)MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap AllocationACM Transactions on Embedded Computing Systems10.1145/352785322:1(1-28)Online publication date: 13-Dec-2022
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Ma CZhou ZHan LShen ZWang YChen RShao Z(2022)Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312317741:10(3276-3289)Online publication date: 1-Oct-2022
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Oh DMoon YLee EHam TPark YLee JAhn JHenkel JLiu X(2021)MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation frameworkProceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3461648.3463844(24-36)Online publication date: 22-Jun-2021
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Aghaei Khouzani HHosseini FYang C(2017)Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261584536:9(1458-1470)Online publication date: 18-Aug-2017
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