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Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

Published: 01 June 2003 Publication History

Abstract

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simuiltaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage convers on from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm2 assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulatior at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-VDD microprocessor is demonstrated to be feasible.

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 11, Issue 3
Special section on the 2001 international conference on computer design (ICCD)
June 2003
223 pages

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2003

Author Tags

  1. buck converter
  2. dc-dc converter
  3. dual supply voltage
  4. high efficiency
  5. integrated inductors
  6. low power
  7. low voltage
  8. modeling of dc-dc converters
  9. monolithic dc-dc conversion
  10. multiple supply voltages
  11. power supply
  12. supply voltage scaling
  13. switching dc-dc converters
  14. voltages regulator

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