research-article

An asynchronous ternary logic signaling system

Authors:

Tomaz Felicijan,

Steve B. FurberAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Issue 6

Pages 1114 - 1119

https://doi.org/10.1109/TVLSI.2003.819571

Published: 01 December 2003 Publication History

Abstract

This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.

References

[1]

J. B. Kuo and J. H. Lou, Low-Voltage CMOS VLSI Circuits. New York: Wiley, 1999.

Google Scholar

[2]

J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design: A System Perspective, Dordrecht, The Netherlands: Kluwer, 2001.

Crossref

Google Scholar

[3]

H. M. Aytac, "Ternary logic based on a novel MOS building block circuit," in Proc. IEEE Int. Symp. Multiple-Valued Logic (ISMVL), May 1983, pp. 20-25.

Google Scholar

[4]

P. Balla and A. Antoniou, "Low power dissipation MOS ternary logic family," IEEE J. Solid-State Circuits, vol. 19, pp. 739-749, Oct. 1984.

Crossref

Google Scholar

[5]

X.Wu and F. Prosser, "CMOS ternary logic circuits," in Proc. Inst. Elect. Eng., vol. 137, Feb. 1990, pp. 21-27.

Google Scholar

[6]

J. S. Wang, C. Y. Wu, and M. K. Tsai, "Low power dynamic ternary logic," Proc. Inst. Elect. Eng., pt. G, vol. 135, no. 6, pp. 221-230, Dec. 1988.

Google Scholar

[7]

R. Mariani, R. Roncella, R. Saletti, and P. Terreni, "On the realization of delay-insensitive asynchronous circuits with CMOS ternary logic," in Proc. 3th Int. Symp. Asynchronous Circuits ASYNC'97, Eindhoven, The Netherlands, 1997, pp. 54-62.

Crossref

Google Scholar

[8]

W. J. Bainbridge, "Asynchronous System-on-Chip Interconnect," Ph.D. dissertation, Dept. Comput. Sci., Univ. Manchester, U.K., 2000.

Google Scholar

[9]

W. Dally and J. Poulton, Digital Systems Engineering, Cambridge, U.K.: Cambridge Univ. Press, 1998.

Crossref

Google Scholar

[10]

W. J. Bainbridge and S. Furber, "CHAIN: A delay-insensitive chip area interconnect," IEEE Micro., vol. 22, pp. 16-23, Sept./Oct. 2002.

Digital Library

Google Scholar

[11]

H. Zhang, V. George, and J. M. Rabaey, "Low-swing on-chip signaling techniques: Effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, pp. 264-272, June 2000.

Digital Library

Google Scholar

Cited By

View all

Amirany AJafari KMoaiyeri M(2021)High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift RegisterIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305598329:5(916-924)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1109/TVLSI.2021.3055983
Beckett PMemon T(2012)Reconfigurable Blocks Based on Balanced TernaryJournal of Signal Processing Systems10.1007/s11265-010-0559-567:1(3-13)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1007/s11265-010-0559-5
Das SDasgupta PSensarma S(2012)Arithmetic algorithms for ternary number systemProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_13(111-120)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_13
Show More Cited By

Recommendations

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals ...
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives ...
Asynchronous gate-diffusion-input (GDI) circuits

Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2 × smaller than CMOS C-elements, 30% faster, and ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 11, Issue 6

December 2003

213 pages

ISSN:1063-8210

Issue’s Table of Contents

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 December 2003

Revised: 15 January 2003

Received: 07 October 2002

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Amirany AJafari KMoaiyeri M(2021)High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift RegisterIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305598329:5(916-924)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1109/TVLSI.2021.3055983
Beckett PMemon T(2012)Reconfigurable Blocks Based on Balanced TernaryJournal of Signal Processing Systems10.1007/s11265-010-0559-567:1(3-13)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1007/s11265-010-0559-5
Das SDasgupta PSensarma S(2012)Arithmetic algorithms for ternary number systemProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_13(111-120)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_13
Rokhani FSobelman G(2010)Bus energy consumption for multilevel signalsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.201617757:1(64-71)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TCSI.2009.2016177
Lee JChoi ECho K(2006)Design of asynchronous embedded processor with new ternary data encoding schemeProceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11796435_40(395-405)Online publication date: 17-Jul-2006
https://dl.acm.org/doi/10.1007/11796435_40

Abstract

References

Cited By

Recommendations

Basic circuits for multi-valued sequential logic

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Asynchronous gate-diffusion-input (GDI) circuits

Comments

Information

Published In

Publisher

Publication History

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Share

Share this Publication link

Share on social media

Affiliations