research-article

Simultaneous switching noise analysis using application specific device modeling

Authors:

Pinaki MazumderAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Issue 6

Pages 1146 - 1152

https://doi.org/10.1109/TVLSI.2003.817548

Published: 01 December 2003 Publication History

Abstract

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and α-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.

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Cited By

Duong QBhide AAlvandpour A(2019)Design and analysis of high-speed split-segmented switched-capacitor DACsAnalog Integrated Circuits and Signal Processing10.1007/s10470-017-0981-892:2(199-217)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-017-0981-8
Shi YHe LScheffer LPhillips JHu A(2010)Modeling and design for beyond-the-die power integrityProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133516(411-416)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133516

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 11, Issue 6

December 2003

213 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2003.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 December 2003

Revised: 27 November 2002

Received: 07 January 2002

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Cited By

Duong QBhide AAlvandpour A(2019)Design and analysis of high-speed split-segmented switched-capacitor DACsAnalog Integrated Circuits and Signal Processing10.1007/s10470-017-0981-892:2(199-217)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-017-0981-8
Shi YHe LScheffer LPhillips JHu A(2010)Modeling and design for beyond-the-die power integrityProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133516(411-416)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133516

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