L<inline-formula><tex-math notation="LaTeX">${}_{\text{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\text{2/2s}}$</tex-math></inline-formula>: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs
Pages 3229 - 3241
Abstract
While it becomes more challenging to improve the energy efficiency of incremental delta-sigma data converters (IDCs) from the analog circuit design perspective, we propose two novel linear reconstruction filters for IDCs to enhance their performance in a digital way, including the L<inline-formula><tex-math notation="LaTeX">${}_{\mathbf{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\mathbf{2}}$</tex-math></inline-formula> filter and its symmetric version, the L<inline-formula><tex-math notation="LaTeX">${}_{\mathbf{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\mathbf{2s}}$</tex-math></inline-formula> filter. Compared to the classical linear reconstruction filters, such as the cascade-of-integrators (CoI) and cascaded integrator-comb (CIC) filter (an implementation of <italic>sinc</italic> filter), the proposed filters can achieve efficient quantization and thermal noise suppression, with the lowest thermal noise penalty factor of 1.2 among the high-order linear reconstruction filters. In this paper, we present analytical, numerical, and experimental results to demonstrate the superior performance of the filters for first-order and second-order IDC output reconstruction. The proposed filters are hardware-friendly and example digital implementations in a standard complementary metal-oxide-semiconductor (CMOS) and field-programmable gate array (FPGA) platforms are included in this paper.
References
[1]
S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta–Sigma Data Converters, 2nd ed. Piscataway, NJ, USA: Wiley-IEEE Press, 2017.
[2]
A. Bhandari, F. Krahmer, and R. Raskar, “On unlimited sampling and reconstruction,” IEEE Trans. Signal Process., vol. 69, no. 21, pp. 3827–3839, Dec. 2020.
[3]
A. Eamaz, K. V. Mishra, F. Yeganegi, and M. Soltanalian, “UNO: Unlimited sampling meets one-bit quantization,” Dec. 2022,.
[4]
L. Jacques, J. N. Laska, P. T. Boufounos, and R. G. Baraniuk, “Robust 1-bit compressive sensing via binary stable embeddings of sparse vectors,” IEEE Trans. Inf. Theory, vol. 59, no. 4, pp. 2082–2102, Jan. 2013.
[5]
A. Eamaz, F. Yeganegi, and M. Soltanalian, “One-bit phase retrieval: More samples means less complexity?” IEEE Trans. Signal Process., vol. 70, pp. 4618–4632, 2022.
[6]
A. Eamaz, F. Yeganegi, and M. Soltanalian, “Covariance recovery for one-bit sampled non-stationary signals with time-varying sampling thresholds,” IEEE Trans. Signal Process., vol. 70, pp. 5222–5236, 2022.
[7]
A. Eamaz, F. Yeganegi, and M. Soltanalian, “Covariance recovery for one-bit sampled stationary signals with time-varying sampling thresholds,” Signal Process., vol. 206, 2023, Art. no. 108899.
[8]
A. Eamaz, F. Yeganegi, and M. Soltanalian, “Modified arcsine law for one-bit sampled stationary signals with time-varying thresholds,” in Proc. IEEE Int. Conf. Acoust. Speech Signal Process. (ICASSP), pp. 5459–5463, 2021.
[9]
A. Eamaz, F. Yeganegi, D. Needell, and M. Soltanalian, “ORKA: Accelerated Kaczmarz algorithms for signal recovery from one-bit samples,” Dec. 2022,.
[10]
O. Ordentlich and U. Erez, “Performance analysis and optimal filter design for sigma–delta modulation via duality with DPCM,” IEEE Trans. Inf. Theory, vol. 65, no. 2, pp. 1153–1164, Feb. 2019.
[11]
J. Markus, “Higher-order incremental delta–sigma analog-to-digital converters,” Ph.D. dissertation, Dept. Meas. Inf. Syst., Budapest Univ. Technol. Econ., Budapest, Hungary, 2005.
[12]
B. Wang, M. K. Law, S. B. Belhaouari, and A. Bermak, “Near-optimal decoding of incremental delta–sigma ADC output,” IEEE Trans. Circuits Syst. I, vol. 67, no. 11, pp. 3670–3680, Nov. 2020.
[13]
J. Wagner, P. Vogelmann, and M. Ortmanns, “On the signal filtering property of CT incremental sigma–delta ADCs,” IEEE Trans. Circuits Syst.II, vol. 66, no. 11, pp. 1780–1784, Nov. 2019.
[14]
M. Zhao et al., “A $4\mu W$ bandwidth/power scalable delta–sigma modulator based on swing-enhanced floating inverter amplifiers,” IEEE J. Solid-State Circuits, vol. 57, no. 3, pp. 709–718, Mar. 2022.
[15]
Y. Zhang, C.-H. Chen, T. He, and G. C. Temes, “A 16 b multi-step incremental analog-to-digital converter with single-opamp multi-slope extended counting,” IEEE J. Solid-State Circuits, vol. 52, no. 4, pp. 1066–1076, Apr. 2017.
[16]
B. Gönen, S. Karmakar, R. van Veldhoven, and K. A. A. Makinwa, “A continuous-time zoom ADC for low-power audio applications,” IEEE J. Solid-State Circuits, vol. 55, no. 4, pp. 1023–1031, Apr. 2020.
[17]
L. Jie, M. Zhan, X. Tang, and N. Sun, “A 0.014mm${}^{2}$ 10kHz-BW zoom-incremental-counting ADC achieving 103dB SNDR and 100dB full-scale CMRR,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2022.
[18]
J. Huang and P. P. Mercier, “A 178.9-dB FoM 128-dB SFDR VCO-based AFE for ExG readouts with a calibration-free differential pulse code modulation technique,” IEEE J. Solid-State Circuits, vol. 56, no. 11, pp. 3236–3246, Nov. 2021.
[19]
S. Kavusi, H. Kakavand, and A. E. Gamal, “On incremental sigma–delta modulation with optimal filtering,” IEEE Trans. Circuits Syst. I, vol. 53, no. 5, pp. 1004–1015, May 2006.
[20]
E. Hogenauer, “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoust., Speech, Signal Process., vol. 29, no. 2, pp. 155–162, Apr. 1981.
[21]
J. Wagner, P. Vogelmann, and M. Ortmanns, “Performance evaluation of incremental sigma–delta ADCs based on their NTF,” IEEE Trans. Circuits Syst.II, vol. 67, no. 12, pp. 2813–2817, Dec. 2020.
[22]
J. Steensgaard et al., “Noise–power optimization of incremental data converters,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 55, no. 5, pp. 1289–1296, Jun. 2008.
[23]
M. Marijan and Z. Ignjatovic, “Non-linear reconstruction of delta–sigma modulated signals: Randomized surrogate constraint decoding algorithm,” IEEE Trans. Signal Process., vol. 61, no. 21, pp. 5361–5373, Nov. 2013.
[24]
M. A. Miled, M. Sawan, and E. Ghafar-Zadeh, “A dynamic decoder for first-order $\Sigma\Delta$ modulators dedicated to lab-on-chip applications,” IEEE Trans. Signal Process., vol. 57, no. 10, pp. 4076–4084, Oct. 2009.
[25]
I. Wiemer and W. Schwarz, “Direct projection decoding algorithm for sigma–delta modulated signals,” IEEE Trans. Signal Process., vol. 53, no. 5, pp. 1807–1814, May 2005.
[26]
L. G. McIlrath, “A robust $O(N\log N)$ algorithm for optimal decoding of first-order $\Sigma$-$\Delta$ sequences,” IEEE Trans. Signal Process., vol. 50, no. 8, pp. 1942–1950, Aug. 2002.
[27]
S. Hein, “A fast block-based nonlinear decoding algorithm for $\Sigma\Delta$ modulators,” IEEE Trans. Signal Process., vol. 43, no. 6, pp. 1360–1367, Jun. 1995.
[28]
Texas Instruments. “Datasheet of AD126x, Rev. C.” 2006. Accessed: Jun. 2023. [Online]. Available: https://www.analog.com/media/en/technical-documentation/data-sheets/AD7760.pdf
[29]
B. Wang and M.-K. Law, “Subranging BJT-based CMOS temperature sensor with a $\pm$ 0.45${}^{\circ}$C inaccuracy (3$\sigma$) from –50 ${}^{\circ}$C to 180 ${}^{\circ}$C and a resolution-FoM of 7.2 pJ$\cdot$K${}^{2}$ at 150 ${}^{\circ}$C,” IEEE J. Solid-State Circuits, vol. 57, no. 12, pp. 3693–3703, Dec. 2022.
[30]
B. Wang, M.-K. Law, and A. Bermak, “On fully differential incremental $\Delta\Sigma$ ADC with initial feedback zeroing and 1.5-bit feedback,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 1–5, Oct. 2020.
[31]
J. Robert and P. Deval, “A second-order high-resolution incremental A/D converter with offset and charge injection compensation,” IEEE J. Solid-State Circuits, vol. 23, pp. 736–741, Jun. 1988.
[32]
W. Chou and R. M. Gray, “Dithering and its effects on sigma–delta and multistage sigma–delta modulation,” IEEE Trans. Inf. Theory, vol. 37, no. 3, pp. 500–513, May 1991.
[33]
R. Lyons, Understanding Digital Signal Processing, 2nd ed. Upper Saddle River, NJ, USA: Prentice Hall, 2004.
[34]
J. Markus, J. Silva, and G. C. Temes, “Theory and applications of incremental $\Delta\Sigma$ converters,” IEEE Trans. Circuits Syst. I, vol. 51, no. 4, pp. 678–690, Apr. 2004.
Recommendations
A 10-<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> Transient Recovery Time Low-EMI DC-DC Buck Converter With <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$\Sigma $ </tex-math></inline-formula> Modulator
This paper presents a 10-<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> transient recovery time and a low electromagnetic interference dc–dc buck converter with a second-order delta–sigma (<inline-...
A 1.2-V 450-μW <inline-formula> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor
A third-order G<sub>m</sub>-C Chebyshev low-pass filter based on a novel gain-boosted tunable transconductor is presented. The transconductor employs local negative feedback for linearization controlling the drain voltage of the input transistors biased ...
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC With AntiPole-Splitting Opamp and Digital <inline-formula> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> Calibration
A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta–sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/.
Publisher
IEEE Press
Publication History
Published: 01 January 2023
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 16 Nov 2024
Other Metrics
Citations
View Options
View options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in