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vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices

Published: 01 July 2017 Publication History

Abstract

I/O is becoming one of major performance bottlenecks in NAND-flash-based mobile devices. Novel nonvolatile memories (NVMs), such as phase change memory and spin-transfer torque random access memory, can provide fast read/write operations. In this paper, we propose a unified NVM/flash architecture to improve the I/O performance. A transparent scheme, virtualized flash (vFlash), is also proposed to manage the unified architecture. Within vFlash, interapp and intra-app techniques are proposed to optimize the application performance by exploiting the historical locality and I/O access patterns of applications. Since vFlash is on the bottom of the I/O stack, the application features will be lost. Therefore, we also propose a cross-layer technique to transfer the application information from the application layer to the vFlash layer. The proposed scheme is evaluated based on an Android platform, and the experimental results show that the proposed scheme can effectively improve the I/O performance of mobile devices.

References

[1]
R. Chen et al., “Unified non-volatile memory and NAND flash memory architecture in smartphones,” in Proc. 20th Asia South Pac. Design Autom. Conf. (ASP-DAC), Tokyo, Japan, 2015, pp. 1–6.
[2]
X. Li, G. Yan, Y. Han, and X. Li, “SmartCap: Using machine learning for power adaptation of smartphone’s application processor,” ACM Trans. Design Autom. Electron. Syst., vol. 20, no. 1, pp. 1–16, 2014.
[3]
C.-H. Tu, H.-H. Hsu, J.-H. Chen, C.-H. Chen, and S.-H. Hung, “Performance and power profiling for emulated android systems,” ACM Trans. Design Autom. Electron. Syst., vol. 19, no. 2, pp. 1–25, 2014.
[4]
J. Boukhobza, P. Olivier, L. Plassart, H. Ouarnoughi, and L. Bellatreche, “Embedded databases on flash memories: Performance and lifetime issues, the case of SQLite,” in Proc. Embedded Real Time Softw. Syst. (ERTSS), Toulouse, France, 2014, pp. 1–8.
[5]
H. Kim, N. Agrawal, and C. Ungureanu, “Revisiting storage for smartphones,” ACM Trans. Stor., vol. 8, no. 4, pp. 1–25, 2012.
[6]
S. Jeong, K. Lee, S. Lee, S. Son, and Y. Won, “I/O stack optimization for smartphones,” in Proc. USENIX Annu. Tech. Conf. (ATC), San Jose, CA, USA, 2013, pp. 309–320.
[7]
Z. Zhang, L. Ju, and Z. Jia, “Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead,” in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Dresden, Germany, 2016, pp. 942–947.
[8]
P.-C. Huang, Y.-H. Chang, K.-Y. Lam, J.-T. Wang, and C.-C. Huang, “Garbage collection for multiversion index in flash-based embedded databases,” ACM Trans. Design Autom. Electron. Syst., vol. 19, no. 3, pp. 1–27, 2014.
[9]
L. Shi et al., “Retention trimming for lifetime improvement of flash memory storage systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 35, no. 1, pp. 58–71, Jan. 2016.
[10]
Y. Chen et al., “A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 560–573, Feb. 2012.
[11]
C. J. Xue et al., “Emerging non-volatile memories: Opportunities and challenges,” in Proc. 7th IEEE/ACM/IFIP Int. Conf. Hardw./Softw. Codesign Syst. Synthesis (CODES+ISSS), Taipei, Taiwan, 2011, pp. 325–334.
[12]
B. Cheng and B. Buzbee, “A JIT compiler for android’s Dalvik VM,” in Proc. Google I/O Developer Conf., 2010, pp. 1–32.
[13]
M. Xia, L. Gong, Y. Lyu, Z. Qi, and X. Liu, “Effective real-time android application auditing,” in Proc. IEEE Symp. Security Privacy, San Jose, CA, USA, 2015, pp. 899–914.
[14]
L. Lu, A. C. Arpaci-Dusseau, R. H. Arpaci-Dusseau, and S. Lu, “A study of Linux file system evolution,” ACM Trans. Stor., vol. 10, no. 1, pp. 1–32, 2014.
[15]
K. Zhong et al., “DR. Swap: Energy-efficient paging for smartphones,” in Proc. Int. Symp. Low Power Electron. Design (ISLPED), La Jolla, CA, USA, 2014, pp. 81–86.
[16]
L.-P. Chang and Y.-C. Su, “Plugging versus logging: A new approach to write buffer management for solid-state disks,” in Proc. 48th Design Autom. Conf. (DAC), San Diego, CA, USA, 2011, pp. 23–28.
[17]
F. Chen, D. A. Koufaty, and X. Zhang, “Understanding intrinsic characteristics and system implications of flash memory based solid state drives,” in Proc. 11th Int. Joint Conf. Measur. Modeling Comput. Syst. (SIGMETRICS), Seattle, WA, USA, 2009, pp. 181–192.
[18]
Y. Wang et al., “A reliability-aware address mapping strategy for NAND flash memory storage systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33, no. 11, pp. 1623–1631, Nov. 2014.
[19]
J. Coburn, T. Bunker, M. Schwarz, R. Gupta, and S. Swanson, “From ARIES to MARS: Transaction support for next-generation, solid-state drives,” in Proc. 24th ACM Symp. Oper. Syst. Principles (SOSP), Farmington, PA, USA, 2013, pp. 197–212.
[20]
T.-W. Kuo, Y.-H. Chang, P.-C. Huang, and C.-W. Chang, “Special issues in flash,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), San Jose, CA, USA, Nov. 2008, pp. 821–826.
[21]
C. Wang and W.-F. Wong, “SAW: System-assisted wear leveling on the write endurance of NAND flash devices,” in Proc. 50th Design Autom. Conf. (DAC), Austin, TX, USA, 2013, pp. 1–9.
[22]
J. Boukhobza et al., “MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management,” J. Syst. Archit., vol. 61, nos. 3–4, pp. 157–171, 2015.
[23]
Y. Hua, B. Xiao, X. Liu, and D. Feng, “The design and implementations of locality-aware approximate queries in hybrid storage systems,” IEEE Trans. Parallel Distrib. Syst., vol. 26, no. 11, pp. 3194–3207, Nov. 2015.
[24]
A. M. Caulfield et al., “Moneta: A high-performance storage array architecture for next-generation, non-volatile memories,” in Proc. 43rd Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO), Atlanta, GA, USA, 2010, pp. 385–395.
[25]
Y. Kim, M. Imani, S. Patil, and T. S. Rosing, “CAUSE: Critical application usage-aware memory system using non-volatile memory for mobile devices,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), Austin, TX, USA, 2015, pp. 690–696.
[26]
X. Dong and Y. Xie, “AdaMS: Adaptive MLC/SLC phase-change memory design for file storage,” in Proc. 16th Asia South Pac. Design Autom. Conf. (ASP-DAC), 2011, pp. 31–36.
[27]
A. Jog et al., “Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs,” in Proc. 49th Annu. Design Autom. Conf. (DAC), San Francisco, CA, USA, 2012, pp. 243–252.
[28]
M. Zhao, L. Jiang, L. Shi, Y. Zhang, and C. J. Xue, “Wear relief for high-density phase change memory through cell morphing considering process variation,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 34, no. 2, pp. 227–237, Feb. 2015.
[29]
R. Wang, L. Jiang, Y. Zhang, and J. Yang, “SD-PCM: Constructing reliable super dense phase change memory under write disturbance,” in Proc. 20th Int. Conf. Archit. Support Program. Lang. Oper. Syst. (ASPLOS), Istanbul, Turkey, 2015, pp. 19–31.
[30]
R. Chen et al., “On-demand block-level address mapping in large-scale NAND flash storage systems,” IEEE Trans. Comput., vol. 64, no. 6, pp. 1729–1741, Jun. 2015.
[31]
L. Jiang, Y. Zhang, and J. Yang, “ER: Elastic reset for low power and long endurance MLC based phase change memory,” in Proc. ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), Redondo Beach, CA, USA, 2012, pp. 39–44.
[32]
D.-W. Chang, H.-H. Chen, D.-J. Yang, and H.-P. Chang, “BLAS: Blocklevel adaptive striping for solid-state drives,” ACM Trans. Design Autom. Electron. Syst., vol. 19, no. 2, pp. 1–29, 2014.
[33]
Micron. (2016). MT66R7072A10AB5ZZW.ZCA TR. [Online]. Available: http://www.ficpdf.com/datasheet/MT66R7072A10AB5ZZW_ZCA%20TR/3039664.html
[34]
Micron. (2016). MT29F2T08CUHBBM4-3R:B. [Online]. Available: http://www.eciaauthorized.com/search/MT29F2T08CUHBBM4-3R-B
[35]
D. Lee et al., “LRFU: A spectrum of policies that subsumes the least recently used and least frequently used policies,” IEEE Trans. Comput., vol. 50, no. 12, pp. 1352–1361, Dec. 2001.
[37]
J. Guo, J. Yang, Y. Zhang, and Y. Chen, “Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer,” in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Grenoble, France, pp. 859–864.
[38]
J. Hu, Q. Zhuge, C. J. Xue, W.-C. Tseng, and E. H.-M. Sha, “Software enabled wear-leveling for hybrid PCM main memory on embedded systems,” in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Grenoble, France, 2013, pp. 599–602.
[39]
Y.-H. Kuan, Y.-H. Chang, P.-C. Huang, and K.-Y. Lam, “Space-efficient multiversion index scheme for PCM-based embedded database systems,” in Proc. 51st ACM/EDAC/IEEE Design Autom. Conf. (DAC), San Francisco, CA, USA, 2014, pp. 1–6.
[40]
M. Zhao, L. Jiang, Y. Zhang, and C. J. Xue, “SLC-enabled wear leveling for MLC PCM considering process variation,” in Proc. 51st Annu. Design Autom. Conf. (DAC), San Francisco, CA, USA, 2014, pp. 1–6.
[41]
P.-L. Wu, Y.-H. Chang, and T.-W. Kuo, “A file-system-aware FTL design for flash-memory storage systems,” in Proc. Conf. Design Autom. Test Europe (DATE), Nice, France, 2009, pp. 393–398.
[42]
Y.-H. Chang, P.-L. Wu, T.-W. Kuo, and S.-H. Hung, “An adaptive file-system-oriented FTL mechanism for flash-memory storage systems,” ACM Trans. Embedded Comput. Syst., vol. 11, no. 1, pp. 1–19, 2012.
[43]
J. Zhao, O. Mutlu, and Y. Xie, “FIRM: Fair and high-performance memory control for persistent memory systems,” in Proc. 47th Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO), Cambridge, U.K., 2014, pp. 153–165.
[44]
Y. Wang et al., “PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 7, pp. 1491–1505, Jul. 2014.
[45]
Y. Wang et al., “A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops,” in Proc. ESSCIRC, Bordeaux, France, 2012, pp. 149–152.
[46]
B. Li, Y. Wang, Y. Wang, Y. Chen, and H. Yang, “Training itself: Mixed-signal training acceleration for memristor-based neural network,” in Proc. IEEE/ACM 19th Asia South Pac. Design Autom. Conf. (ASP-DAC), Singapore, 2014, pp. 361–366.
[47]
B. Li, Y. Wang, Y. Chen, H. Li, and H. Yang, “ICE: Inline calibration for memristor crossbar-based computing engine,” in Proc. Conf. Design Autom. Test Europe (DATE), Dresden, Germany, 2014, pp. 1–4.
[48]
Y. Wang, B. Li, R. Luo, Y. Chen, N. Xu, and H. Yang, “Energy efficient neural networks for big data analytics,” in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Dresden, Germany, 2014, pp. 1–2.
[49]
I. Issenin, E. Brockmeyer, M. Miranda, and N. Dutt, “DRDU: A data reuse analysis technique for efficient scratch-pad memory management,” ACM Trans. Design Autom. Electron. Syst., vol. 12, no. 2, 2007, Art. no.
[50]
Z. Zhou, L. Ju, Z. Jia, and X. Li, “Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systems,” in Proc. 20th Asia South Pac. Design Autom. Conf. (ASP-DAC), 2015, pp. 423–428.

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  • (2022)Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile MemoryACM Transactions on Architecture and Code Optimization10.1145/351170619:2(1-26)Online publication date: 24-Mar-2022

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      cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 36, Issue 7
      July 2017
      175 pages

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      IEEE Press

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      Published: 01 July 2017

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      • (2022)Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile MemoryACM Transactions on Architecture and Code Optimization10.1145/351170619:2(1-26)Online publication date: 24-Mar-2022

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