research-article

Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis

Authors:

Krishnendu Chakrabarty,

Xinli GuAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34, Issue 6

Pages 1014 - 1026

https://doi.org/10.1109/TCAD.2015.2399438

Published: 01 June 2015 Publication History

Abstract

Reasoning-based functional-fault diagnosis has recently been advocated to achieve high diagnosis accuracy, low defect escapes, and reducing manufacturing cost. However, such diagnosis method requires a rich set of test items (syndromes) and a sizable database of faulty boards to learn from. An insufficient number of failed boards, ambiguous root-cause identification, and redundant or irrelevant syndromes can render reasoning-based diagnosis ineffective. Periodic evaluation and analysis can help locate weaknesses in a diagnosis system and thereby provide guidelines for redesigning the tests, which facilitates better diagnosis. We propose an information-theoretic framework for evaluating the effectiveness of and providing guidance to a reasoning-based functional-fault diagnosis system. Syndrome analysis based on feature selection methods provides a representative set of syndromes and suggests irrelevant syndromes in diagnosis. Root-cause analysis measures the discriminative ability of differentiating a given root cause from others. Results are presented for four types of diagnosis systems for three complex boards that are in volume production.

References

[1]

T. Vo et al., “Design for board and system level structural test and diagnosis,” in Proc. IEEE Int. Test Conf., Santa Clara, CA, USA, Nov. 2006, pp. 1–10.

[2]

B. Benware et al., “Fault diagnosis with orthogonal compactors in scan-based designs,” J. Electron. Test. Theory Appl., vol. 27, no. 5, pp. 599–609, 2011.

Digital Library

[3]

K. P. Parker, “Defect coverage of boundary-scan tests: What does it mean when a boundary-scan test passes?” in Proc. IEEE Int. Test Conf., Charlotte, NC, USA, Nov. 2003, pp. 181–189.

[4]

F. G. Zadegan, U. Ingelsson, E. Larsson, and G. Carlsson, “Reusing and retargeting on-chip instrument access procedures in IEEE P1687,” IEEE Design Test Comput., vol. 29, no. 2, pp. 79–88, Apr. 2012.

[5]

D. Manley and B. Eklow, “A model based automated debug process,” in Proc. IEEE Board Test Workshop, Baltimore, MD, USA, 2002, pp. 1–7.

[6]

W. G. Fenton, T. M. McGinnity, and L. P. Maguire, “Fault diagnosis of electronic systems using intelligent techniques: A review,” IEEE Trans. Syst., Man, Cybern. C, Appl. Rev., vol. 31, no. 3, pp. 269–281, Aug. 2001.

Digital Library

[7]

C. O’Farrill, M. Moakil-Chbany, and B. Eklow, “Optimized reasoning-based diagnosis for non-random, board-level, production defects,” in Proc. IEEE Int. Test Conf., Austin, TX, USA, Nov. 2005, pp. 173–179.

[8]

F. Ye, Z. Zhang, K. Chakrabarty, and X. Gu, “Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis,” in Proc. IEEE Eur. Test Symp., Avignon, France, 2013, pp. 1–6.

[9]

F. Ye, K. Chakrabarty, Z. Zhang, and X. Gu, “Information-theoretic framework for evaluating and guiding board-level functional-fault diagnosis,” IEEE Design Test Comput., vol. 31, no. 3, pp. 65–75, Jun. 2014.

[10]

L. Amati et al., “An incremental approach to functional diagnosis,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT), Chicago, IL, USA, 2009, pp. 392–400.

[11]

C. Bolchini, E. Quintarelli, F. Salice, and P. Garza, “A data mining approach to incremental adaptive functional diagnosis,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst. (DFT), New York, NY, USA, 2013, pp. 13–18.

[12]

F. Ye, Z. Zhang, K. Chakrabarty, and X. Gu, “Board-level functional fault diagnosis using artificial neural networks, support-vector machines, and weighted-majority voting,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 5, pp. 723–736, May 2013.

Digital Library

[13]

F. Ye, Z. Zhang, K. Chakrabarty, and X. Gu, “Adaptive board-level functional fault diagnosis using decision trees,” in Proc. IEEE Asian Test Symp., Niigata, Japan, Oct. 2012, pp. 202–207.

[14]

Z. Sun et al., “AgentDiag: An agent-assisted diagnostic framework for board-level functional failures,” in Proc. IEEE Int. Test Conf., Anaheim, CA, USA, 2013, pp. 1–8.

[15]

Z. Zhang, Z. Wang, X. Gu, and K. Chakrabarty, “Physical-defect modeling and optimization for fault-insertion test,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 723–736, Apr. 2012.

Digital Library

[16]

H. Peng, F. Long, and C. Ding, “Feature selection based on mutual information criteria of max-dependency, max-relevance, and min-redundancy,” IEEE Trans. Pattern Anal. Mach. Intell., vol. 27, no. 8, pp. 1226–1238, Aug. 2005.

Digital Library

[17]

A. Webb, Statistical Pattern Recognition. Chichester, U.K.: Wiley, 2003.

[18]

E. Oja, A. Hyvarinen, and J. Karhunen, Independent Component Analysis. New York, NY, USA: Wiley, 2001.

[19]

T. Cover and J. Thomas, Elements of Information Theory. Hoboken, NJ, USA: Wiley, 2006.

Digital Library

[20]

J. Rissanen, “Modeling by shortest data description,” Automatica, vol. 14, no. 5, pp. 465–471, 1978.

Digital Library

[21]

M. A. Hall, “Correlation-based feature selection for machine learning,” Ph.D. dissertation, Dept. Comput. Sci., University of Waikato, Hamilton, New Zealand, 1999.

[22]

M. Hall et al., “The WEKA data mining software: An update,” ACM SIGKDD Explor. Newslett., vol. 11, no. 1, pp. 10–18, 2009.

Digital Library

[23]

F. Ye, K. Chakrabarty, Z. Zhang, and X. Gu, “Knowledge discovery and knowledge transfer in board-level functional fault diagnosis,” in Proc. IEEE Int. Test Conf., Seattle, WA, USA, 2014, pp. 1–10.

Cited By

Pichette SThibeault C(2023)Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322228742:7(2404-2417)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3222287
Hao SLiu YWang YWang YZhe WZhang ARangwala H(2022)Three-Stage Root Cause Analysis for Logistics Time Efficiency via Explainable Machine LearningProceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining10.1145/3534678.3539024(2987-2996)Online publication date: 14-Aug-2022
https://dl.acm.org/doi/10.1145/3534678.3539024

Index Terms

Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis

Index terms have been assigned to the content through auto-classification.

Recommendations

Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees
ATS '12: Proceedings of the 2012 IEEE 21st Asian Test Symposium

Functional fault diagnosis at board-level is desirable for high-volume production since it improves product yield. However, to ensure diagnosis accuracy and effective board repair, a large number of syndromes must be used. Therefore, the diagnosis cost ...
Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis
ATS '13: Proceedings of the 2013 22nd Asian Test Symposium

Functional fault diagnosis is widely used in board manufacturing to ensure product quality and improve product yield. Advanced machine-learning techniques have recently been advocated for reasoning-based diagnosis, these technologies are based on ...
Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines
ATS '12: Proceedings of the 2012 IEEE 21st Asian Test Symposium

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis based on the historical data of successfully repaired boards. However, the training complexity increases ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 34, Issue 6

June 2015

170 pages

ISSN:0278-0070

Issue’s Table of Contents

Copyright © 2015.

Publisher

IEEE Press

Publication History

Published: 01 June 2015

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Pichette SThibeault C(2023)Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322228742:7(2404-2417)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3222287
Hao SLiu YWang YWang YZhe WZhang ARangwala H(2022)Three-Stage Root Cause Analysis for Logistics Time Efficiency via Explainable Machine LearningProceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining10.1145/3534678.3539024(2987-2996)Online publication date: 14-Aug-2022
https://dl.acm.org/doi/10.1145/3534678.3539024

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents