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A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors

Published: 01 April 2011 Publication History

Abstract

A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.

Cited By

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  • (2018)Determining Effective Shortest Path in Asynchronous Network-on-Chip Through Bio-Inspired Optimization TechniquesWireless Personal Communications: An International Journal10.1007/s11277-018-5373-6102:4(3375-3392)Online publication date: 1-Oct-2018
  • (2017)Closing the Accuracy Gap of Static Performance Analysis of Asynchronous CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062211(1-6)Online publication date: 18-Jun-2017
  • (2016)Reconfigurable Links for Self-Timed On-Chip CommunicationProceedings of the 9th International Workshop on Network on Chip Architectures10.1145/2994133.2994141(15-20)Online publication date: 15-Oct-2016
  • Show More Cited By

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Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 30, Issue 4
April 2011
163 pages

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IEEE Press

Publication History

Published: 01 April 2011

Author Tags

  1. Asynchronous design
  2. GALS
  3. low power
  4. network-on-chip
  5. parallel processing
  6. transition-signaling

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Cited By

View all
  • (2018)Determining Effective Shortest Path in Asynchronous Network-on-Chip Through Bio-Inspired Optimization TechniquesWireless Personal Communications: An International Journal10.1007/s11277-018-5373-6102:4(3375-3392)Online publication date: 1-Oct-2018
  • (2017)Closing the Accuracy Gap of Static Performance Analysis of Asynchronous CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062211(1-6)Online publication date: 18-Jun-2017
  • (2016)Reconfigurable Links for Self-Timed On-Chip CommunicationProceedings of the 9th International Workshop on Network on Chip Architectures10.1145/2994133.2994141(15-20)Online publication date: 15-Oct-2016
  • (2016)Achieving lightweight multicast in asynchronous networks-on-chip using local speculationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897978(1-6)Online publication date: 5-Jun-2016
  • (2015)A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC'sProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744777(1-6)Online publication date: 7-Jun-2015
  • (2014)WaveSyncACM Transactions on Design Automation of Electronic Systems10.1145/264795019:4(1-22)Online publication date: 29-Aug-2014
  • (2013)Low-power networks-on-chipProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648700(132-134)Online publication date: 4-Sep-2013
  • (2013)A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485370(332-337)Online publication date: 18-Mar-2013
  • (2013)TornadoNoCACM Transactions on Architecture and Code Optimization10.1145/2541228.255531210:4(1-30)Online publication date: 1-Dec-2013

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