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Automating Technology Relative Logic Synthesis and Module Selection

Published: 01 November 2006 Publication History

Abstract

This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 2, Issue 2
November 2006
74 pages

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IEEE Press

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Published: 01 November 2006

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