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CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

Published: 01 September 2014 Publication History

Abstract

Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy of future computer systems. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6–10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM have been suggested. In this paper, we present a new memory management technique for hybrid PCM and DRAM memory architecture that efficiently hides the slow write performance of PCM. Specifically, we aim to estimate future write references accurately and then absorb frequent memory writes into DRAM. To do this, we analyze the characteristics of memory write references and find two noticeable phenomena. First, using write history alone performs better than using both read and write history in estimating future write references. Second, the frequency characteristic is a better estimator than temporal locality in predicting future memory writes. Based on these two observations, we present a new page replacement algorithm called CLOCK-DWF (CLOCK with Dirty bits and Write Frequency) that significantly reduces the number of write operations that occur on PCM and also increases the lifespan of PCM memory.

Cited By

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  • (2024)Trimma: Trimming Metadata Storage and Latency for Hybrid Memory SystemsProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3689612(108-120)Online publication date: 14-Oct-2024
  • (2024)Intelligent Page Migration on Heterogeneous Memory by Using TransformerInternational Journal of Parallel Programming10.1007/s10766-024-00776-x52:5-6(380-399)Online publication date: 1-Dec-2024
  • (2023)Cooperative Buffer Management With Fine-Grained Data Migrations for Hybrid Memory SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321020142:6(1838-1851)Online publication date: 1-Jun-2023
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cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 63, Issue 9
September 2014
266 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 September 2014

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Cited By

View all
  • (2024)Trimma: Trimming Metadata Storage and Latency for Hybrid Memory SystemsProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3689612(108-120)Online publication date: 14-Oct-2024
  • (2024)Intelligent Page Migration on Heterogeneous Memory by Using TransformerInternational Journal of Parallel Programming10.1007/s10766-024-00776-x52:5-6(380-399)Online publication date: 1-Dec-2024
  • (2023)Cooperative Buffer Management With Fine-Grained Data Migrations for Hybrid Memory SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321020142:6(1838-1851)Online publication date: 1-Jun-2023
  • (2022)FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance OptimizationsACM Transactions on Architecture and Code Optimization10.1145/356588520:1(1-26)Online publication date: 16-Dec-2022
  • (2022)Rethinking the Interactivity of OS and Device Layers in Memory ManagementACM Transactions on Embedded Computing Systems10.1145/353087621:4(1-21)Online publication date: 23-Aug-2022
  • (2022)SRS-MigProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530327(217-222)Online publication date: 6-Jun-2022
  • (2022)Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory SystemIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.312353933:7(1666-1677)Online publication date: 1-Jul-2022
  • (2022)TransMigrator: A Transformer-Based Predictive Page Migration Mechanism for Heterogeneous MemoryNetwork and Parallel Computing10.1007/978-3-031-21395-3_17(180-191)Online publication date: 24-Sep-2022
  • (2021)Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight ApproximationACM Transactions on Embedded Computing Systems10.1145/347701620:5s(1-21)Online publication date: 22-Sep-2021
  • (2021)Monolithically Integrating Non-Volatile Main Memory over the Last-Level CacheACM Transactions on Architecture and Code Optimization10.1145/346263218:4(1-26)Online publication date: 17-Jul-2021
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