research-article

Pseudorandom Testing

Authors:

Kenneth D. Wagner,

Cary K. Chin,

Edward J. McCluskeyAuthors Info & Claims

IEEE Transactions on Computers, Volume 36, Issue 3

Pages 332 - 343

https://doi.org/10.1109/TC.1987.1676905

Published: 01 March 1987 Publication History

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Abstract

Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile.

References

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Cited By

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Suryasarman VBiswas SSahu A(2019)RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05825-935:5(695-714)Online publication date: 1-Oct-2019
Wu SJandhyala SMalaiya YJayasumana A(2008)Antirandom testingVLSI Design10.1155/2008/1657092008:2(1-9)Online publication date: 1-Jan-2008
Wang LWu CWen X(2006)VLSI Test Principles and ArchitecturesundefinedOnline publication date: 14-Aug-2006
Show More Cited By

Index Terms

Pseudorandom Testing

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Reviews

Reviewer: Scott Davidson

Circuits designed using built-in self test (BIST) techniques often use a linear feedback shift register (LFSR) for pattern generation. This has been modeled as a random process, but a pseudorandom process (sampling without replacement) is closer to the way a LFSR functions. This paper compares measures of test quality under the random and pseudorandom models. An important issue in BIST is the length of a test necessary to achieve a certain level of test quality, or the quality of a test of a certain length. The usual quality measurement technique of fault simulation is impractical because of long test lengths, so probabilistic measures must be used. The measures presented in this paper for the pseudorandom model are expected fault coverage; test confidence—the probability that a particular fault will be detected by the test; expected test length to detect a particular fault; weighted test confidence, which includes a measure of the probability that a fault will really occur; and the probability that a test will provide 100 percent fault coverage. All of these are test quality measures that have been used for the random model. These measures all require knowledge of the detectability of each fault, which is the number of possible vectors that will cause the fault to be detected. To find this, either fault simulation or a test generation algorithm is required. Both techniques are computationally very expensive. Though testability measures may pinpoint the more important fault classes, these test quality measures do not let you escape the cost of test evaluation. Comparison of the random and pseudorandom models gives the welcome result that the more accurate pseudorandom model has a shorter required test length for a given expected fault coverage. Another result is that hard-to-detect faults have the greatest impact on test length, and the difference between the models is greatest for just these faults. The paper is important for its comparison of the models, and it is also useful as a good overview of test quality measures for BIST.

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 36, Issue 3

March 1987

135 pages

ISSN:0018-9340

Editor:
Ming T. Liu

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IEEE Computer Society

United States

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Published: 01 March 1987

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Suryasarman VBiswas SSahu A(2019)RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05825-935:5(695-714)Online publication date: 1-Oct-2019
Wu SJandhyala SMalaiya YJayasumana A(2008)Antirandom testingVLSI Design10.1155/2008/1657092008:2(1-9)Online publication date: 1-Jan-2008
Wang LWu CWen X(2006)VLSI Test Principles and ArchitecturesundefinedOnline publication date: 14-Aug-2006
Krasniewski A(2003)Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAsJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(03)00066-349:4-6(283-296)Online publication date: 1-Sep-2003
Chen CHermida RAboulhamid E(2001)Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faultsProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500051(203-208)Online publication date: 30-Sep-2001
Raina RNjinda CMolyneaux R(1997)How Seriously Do You Take Possible-Detect Faults?Proceedings of the 1997 IEEE International Test Conference10.5555/844384.845848Online publication date: 1-Nov-1997
Prepin VDavid R(1997)Fault coverage of a long random test sequence estimated from a short simulationProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836404Online publication date: 27-Apr-1997
Kashiwagi H(1997)Fault diagnosis of a logical circuit by use of a pseudorandom signal and a neural networkArtificial Life and Robotics10.1007/BF024711351:4(169-172)Online publication date: 1-Dec-1997
Majumdar AVrudhula S(1995)Fault Coverage and Test Length Estimation for Random Pattern TestingIEEE Transactions on Computers10.1109/12.36453544:2(234-247)Online publication date: 1-Feb-1995
Krasniewski AWroński LMermet J(1994)Tests for path delay faults vs. tests for gate delay faultsProceedings of the conference on European design automation10.5555/198174.198272(310-315)Online publication date: 23-Sep-1994
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Abstract

References

Cited By

Index Terms

Recommendations

Test Length for Pseudorandom Testing

SAT-based generation of compressed skewed-load tests for transition delay faults

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume

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Access critical reviews of Computing literature here

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