Article

Hardware Supported Time Synchronization in Multi-core Architectures

Authors:

Elizabeth Whitaker Lynch,

George F. RileyAuthors Info & Claims

PADS '09: Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation

Pages 88 - 94

https://doi.org/10.1109/PADS.2009.19

Published: 22 June 2009 Publication History

Abstract

We present a design for a hardware supported global synchronization unit that would be implemented on–chip and directly accessible by all processors in a multi–core architecture. This global synchronization unit will provide all processors with access to global state information from all other processors in just a few clock ticks, and can be used to perform highly efficient and scalable time synchronization for parallel simulations. Further, our design takes into account the possibility of transient messages, and allows for non–uniform look ahead between processors in conservative synchronization methods. Simulating this hardware in a system simulator, we demonstrate its ability to decrease the runtime of a low–look ahead network simulation by a factor of two over a shared–memory barrier synchronization.

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Cited By

Swenson BRiley G(2012)A New Approach to Zero-Copy Message Passing with Reversible Memory Allocation in Multi-core ArchitecturesProceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2012.3(44-52)Online publication date: 15-Jul-2012
https://dl.acm.org/doi/10.1109/PADS.2012.3

Index Terms

Hardware Supported Time Synchronization in Multi-core Architectures

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cover image ACM Conferences

PADS '09: Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation

June 2009

152 pages

ISBN:9780769537139

Sponsors

SIGSIM: ACM Special Interest Group on Simulation and Modeling

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IEEE Computer Society

United States

Publication History

Published: 22 June 2009

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multi-core synchronization

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Cited By

Swenson BRiley G(2012)A New Approach to Zero-Copy Message Passing with Reversible Memory Allocation in Multi-core ArchitecturesProceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2012.3(44-52)Online publication date: 15-Jul-2012
https://dl.acm.org/doi/10.1109/PADS.2012.3

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