Exploring Memory Persistency Models for GPUs
Pages 310 - 322
Abstract
Given its high integration density, high speed, byte addressability, and low standby power, non-volatile or persistent memory is expected to supplement/replace DRAM as main memory. Through persistency programming models (which define durability ordering of stores) and durable transaction constructs, the programmer can provide recoverable data structure (RDS) which allows programs to recover to a consistent state after a failure. While persistency models have been well studied for CPUs, they have been neglected for graphics processing units (GPUs). Considering the importance of GPUs as a dominant accelerator for high performance computing, we investigate persistency models for GPUs.
GPU applications exhibit substantial differences with CPUs applications, hence in this paper we adapt, re-architect, and optimize CPU persistency models for GPUs. We design a pragma-based compiler scheme to express persistency models for GPUs. We identify that the thread hierarchy in GPUs offers intuitive scopes to form epochs and durable transactions. We find that undo logging produces significant performance overheads. We propose to use idempotency analysis to reduce both logging frequency and the size of logs. Through both real-system and simulation evaluations, we show low overheads of our proposed architecture support.
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Published In
September 2019
521 pages
ISBN:9781728136134
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- IFIP WG 10.3: IFIP WG 10.3
- SIGARCH: ACM Special Interest Group on Computer Architecture
- IEEE-CS\DATC: IEEE Computer Society
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IEEE Press
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Published: 26 November 2024
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PACT '19
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- SIGARCH
- IEEE-CS\DATC
PACT '19: International Conference on Parallel Architectures and Compilation Techniques
September 23 - 26, 2019
WA, Seattle, USA
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