research-article

MASR: A Modular Accelerator for Sparse RNNs

Authors:

Brandon Reagen,

Lillian Pentecost,

Alexander M. Rush,

David BrooksAuthors Info & Claims

PACT '19: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques

Pages 1 - 14

https://doi.org/10.1109/PACT.2019.00009

Published: 26 November 2024 Publication History

Abstract

Recurrent neural networks (RNNs) are becoming the de facto solution for speech recognition. RNNs exploit long-term temporal relationships in data by applying repeated, learned transformations. Unlike fully-connected (FC) layers with single vector matrix operations, RNN layers consist of hundreds of such operations chained over time. This poses challenges unique to RNNs that are not found in convolutional neural networks (CNNs) or FC models, namely large dynamic activation. In this paper we present MASR, a principled and modular architecture that accelerates bidirectional RNNs for on-chip ASR. MASR is designed to exploit sparsity in both dynamic activations and static weights. The architecture is enhanced by a series of dynamic activation optimizations that enable compact storage, ensure no energy is wasted computing null operations, and maintain high MAC utilization for highly parallel accelerator designs. In comparison to current state-of-the-art sparse neural network accelerators (e.g., EIE), MASR provides 2× area 3× energy, and 1.6× performance benefits. The modular nature of MASR enables designs that efficiently scale from resource-constrained low-power IoT applications to large-scale, highly parallel datacenter deployments.

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Cited By

Boroumand AGhose SAkin BNarayanaswami ROliveira GMa XShiu EMutlu O(2021)Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference BottlenecksProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00019(159-172)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00019
Kim JHur SLee ELee SKim J(2021)NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP ModelsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00013(75-89)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00013

Index Terms

MASR: A Modular Accelerator for Sparse RNNs
1. Computer systems organization
2. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators

Index terms have been assigned to the content through auto-classification.

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cover image ACM Conferences

PACT '19: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques

September 2019

521 pages

ISBN:9781728136134

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IFIP WG 10.3: IFIP WG 10.3
SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\DATC: IEEE Computer Society

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Published: 26 November 2024

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PACT '19: International Conference on Parallel Architectures and Compilation Techniques

September 23 - 26, 2019

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Cited By

Boroumand AGhose SAkin BNarayanaswami ROliveira GMa XShiu EMutlu O(2021)Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference BottlenecksProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00019(159-172)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00019
Kim JHur SLee ELee SKim J(2021)NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP ModelsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00013(75-89)Online publication date: 26-Sep-2021
https://dl.acm.org/doi/10.1109/PACT52795.2021.00013

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