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Fairness Metrics for Multi-Threaded Processors

Published: 01 January 2011 Publication History

Abstract

Multi-threaded processors execute multiple threads concurrently in order to increase overall throughput. It is well documented that multi-threading affects per-thread performance but, more importantly, some threads are affected more than others. This is especially troublesome for multi-programmed workloads. Fairness metrics measure whether all threads are affected equally. However defining equal treatment is not straightforward. Several fairness metrics for multi-threaded processors have been utilized in the literature, although there does not seem to be a consensus on what metric does the best job of measuring fairness. This paper reviews the prevalent fairness metrics and analyzes their main properties. Each metric strikes a different trade-off between fairness in the strict sense and throughput. We categorize the metrics with respect to this property. Based on experimental data for SMT processors, we suggest using the minimum fairness metric in order to balance fairness and throughput.

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  • (2023)COBRRA: COntention-aware cache Bypass with Request-Response ArbitrationACM Transactions on Embedded Computing Systems10.1145/363274823:1(1-30)Online publication date: 17-Nov-2023
  • (2023)CABARRE: Request Response Arbitration for Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/360809622:5s(1-24)Online publication date: 31-Oct-2023
  • (2023)Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA MulticoresIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.330999934:11(2928-2945)Online publication date: 30-Aug-2023
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Information & Contributors

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Published In

cover image IEEE Computer Architecture Letters
IEEE Computer Architecture Letters  Volume 10, Issue 1
January 2011
28 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 January 2011

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  1. Parallel Architectures
  2. Performance of Systems

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Cited By

View all
  • (2023)COBRRA: COntention-aware cache Bypass with Request-Response ArbitrationACM Transactions on Embedded Computing Systems10.1145/363274823:1(1-30)Online publication date: 17-Nov-2023
  • (2023)CABARRE: Request Response Arbitration for Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/360809622:5s(1-24)Online publication date: 31-Oct-2023
  • (2023)Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA MulticoresIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.330999934:11(2928-2945)Online publication date: 30-Aug-2023
  • (2021)Compounding barriers to fairness in the digital technology ecosystem2021 IEEE International Symposium on Technology and Society (ISTAS)10.1109/ISTAS52410.2021.9629166(1-5)Online publication date: 28-Oct-2021
  • (2018)MASKACM SIGPLAN Notices10.1145/3296957.317316953:2(503-518)Online publication date: 19-Mar-2018
  • (2018)MASKProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173169(503-518)Online publication date: 19-Mar-2018
  • (2018)FLINProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00041(397-410)Online publication date: 2-Jun-2018
  • (2017)Automatic Construction of Program-Optimized FPGA Memory NetworksProceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3020078.3021748(125-134)Online publication date: 22-Feb-2017
  • (2016)Distributed fair scheduling for many-coresProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971895(379-384)Online publication date: 14-Mar-2016
  • (2016)DASHACM Transactions on Architecture and Code Optimization10.1145/284725512:4(1-28)Online publication date: 4-Jan-2016
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