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10.1109/ISDEA.2012.132guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Design and Implementation of a DDR3-based Memory Controller

Published: 16 January 2013 Publication History

Abstract

Memory performance has become the major bottleneck to improve the overall performance of the computer system. DDR3 SDRAM is a new generation of memory technology standard introduced by JEDEC, support multibank in parallel and open-page technology. On the basis of in-depth study of DDR3 timing specification, design a DDR3-based memory controller. Memory access control module is the most key component of the memory controller. Using the stream test bench evaluate the performance, experimental results show that the memory controller of our design can correctly schedule memory access transaction, improve memory bandwidth.

Cited By

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  • (2014)Refresh-aware DDR3 barrel memory controller with deterministic functionalityProceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems10.1145/2568326.2568329(3-9)Online publication date: 15-Feb-2014

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Published In

cover image Guide Proceedings
ISDEA '13: Proceedings of the 2013 Third International Conference on Intelligent System Design and Engineering Applications
January 2013
1556 pages
ISBN:9780769549231

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 January 2013

Author Tags

  1. DDR3 SDRAM
  2. memory access scheduling
  3. memory bandwidth
  4. memory controller

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Cited By

View all
  • (2014)Refresh-aware DDR3 barrel memory controller with deterministic functionalityProceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems10.1145/2568326.2568329(3-9)Online publication date: 15-Feb-2014

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