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Implementing Cross-Device Atomics in Heterogeneous Processors

Published: 25 May 2015 Publication History

Abstract

In this paper we describe how to support atomics across multiple devices in heterogeneous processors. Specifically, this paper provides an overview of how OpenCL 2.0 and Heterogeneous System Architecture (HSA) atomics are supported on integrated CPU-GPU processors called Accelerated Processing Units (APUs). Recently, the C11 and C++11 standards have introduced atomics and an associated memory model for supporting scalable parallel programming with memory consistency semantics. OpenCL 2.0 revision has extended these atomics for multiple devices each one of which can be a CPU or a GPU. The HSA Foundation in the HSA intermediate language (HSAIL) standard has also included support for various atomic operations that span multiple devices. All of these paradigms enable parallel threads running simultaneously on the CPU and GPU cores to synchronize using atomics that were not possible earlier. In APUs, the CPU and GPU cores are on the same die and can access a unified memory. Hence, such a platform provides an excellent opportunity for showcasing the power of OpenCL 2.0/HSA atomics across devices (henceforth referred to as cross-device atomics). In this work we show how we have added capabilities in our LLVM-based OpenCL compiler and a JIT-like finalizer to support cross-device atomics for APUs. Also, by supporting the new HSAIL atomic virtual operations in our finalizer, we have enabled the capability whereby other high-level languages which translate to HSAIL can support cross-device atomics as part of their evolving language standard. Our compiler is one of the first to support such cross-device atomics.

Cited By

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  • (2019)Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA ArchitecturesProceedings of the 2019 ACM/SPEC International Conference on Performance Engineering10.1145/3297663.3310305(79-90)Online publication date: 4-Apr-2019
  • (2018)High-Performance Computation of Bézier Surfaces on Parallel and Heterogeneous PlatformsInternational Journal of Parallel Programming10.1007/s10766-017-0506-146:6(1035-1062)Online publication date: 1-Dec-2018

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Published In

cover image Guide Proceedings
IPDPSW '15: Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop
May 2015
1256 pages
ISBN:9781467376846

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IEEE Computer Society

United States

Publication History

Published: 25 May 2015

Author Tags

  1. Atomics
  2. LLVM
  3. OpenCL
  4. heterogeneous processors
  5. lockfree programming
  6. memory consistency
  7. memory order
  8. memory scope

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Cited By

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  • (2019)Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA ArchitecturesProceedings of the 2019 ACM/SPEC International Conference on Performance Engineering10.1145/3297663.3310305(79-90)Online publication date: 4-Apr-2019
  • (2018)High-Performance Computation of Bézier Surfaces on Parallel and Heterogeneous PlatformsInternational Journal of Parallel Programming10.1007/s10766-017-0506-146:6(1035-1062)Online publication date: 1-Dec-2018

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