A high area-and-energy efficiency 12-bit column-parallel SAR/SS ADC for high-speed infrared focal plane readout circuits with error correction

This paper presents a high-energy-efficiency and high-area-efficiency 12-bit column-parallel successive-approximation-register/single-slope analog-to-digital converter (SAR/SS ADC) for high-speed infrared focal plane readout circuits. The proposed SAR/SS ADC divides the quantization process into upper 8-bit coarse conversion by the SAR ADC and lower 4-bit fine conversion by the SS ADC. The SAR ADC uses the scaled reference-voltage technique to achieve 8-bit conversion using only a 4-bit capacitor DAC. In addition, the SS ADC is designed with an additional 1-bit redundant bit to reduce settling error mismatch between coarse and fine conversion by the proposed error correction method. The proposed SAR/SS ADC is designed in a 0 . 18 μ m CMOS process, and each column occupies an area of 30 μ m × 487 μ m. The post-layout simulation results show that the SAR/SS consumes 73.15 μW for each column and has a DNL of −0.5/+0.6 LSB and an INL of −0.6/+0.4 LSB. The FoM is only 35.72 fJ/step with 2 μ s conversion time, which achieves an appropriate trade-off between conversion speed, power consumption, and area.