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Improvement of trace-driven I-Cache timing attack on the RSA algorithm

Published: 01 January 2013 Publication History

Abstract

The previous I-Cache timing attacks on the RSA algorithm which exploit the instruction path of a cipher are mostly proof-of-concept, and it is harder to put them into practice than D-Cache timing attacks. We propose a trace-driven timing attack model on the RSA algorithm via spying on the whole I-Cache, instead of the partial instruction cache to which the multiplication function mapped, by analyzing the complications in the previous I-Cache timing attack on the RSA algorithm. Then, an improved analysis algorithm of the exponent using the characteristic of the window size in SWE algorithm is provided, which could further reduce the search space of the key bits than the former. We further demonstrate how to recover the private key d from the scattered known bits of d"p and d"q, through demonstrating some conclusions and validating it by experimentation. In addition, an error detection mechanism to detect some erroneous decisions of the operation sequences is provided to reduce the number of the erroneous recovered bits, and improve the precision of decision. We implement an I-Cache timing attack on RSA of OpenSSL in a practical environment, the experimental results show that the feasibility and effectiveness of I-Cache timing attack can be improved.

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  • (2018)Are Timing-Based Side-Channel Attacks Feasible in Shared, Modern Computing Hardware?International Journal of Organizational and Collective Intelligence10.4018/IJOCI.20180401038:2(32-59)Online publication date: 1-Apr-2018
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Information & Contributors

Information

Published In

cover image Journal of Systems and Software
Journal of Systems and Software  Volume 86, Issue 1
January, 2013
247 pages

Publisher

Elsevier Science Inc.

United States

Publication History

Published: 01 January 2013

Author Tags

  1. Error detection
  2. Instruction cache timing attacks
  3. RSA cryptographic algorithm
  4. Side-channel attacks
  5. Trace-driven

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Cited By

View all
  • (2023)Transient-Execution Attacks: A Computer Architect PerspectiveACM Computing Surveys10.1145/360361956:3(1-38)Online publication date: 6-Oct-2023
  • (2021)Bit-level color image encryption algorithm based on coarse-grained logistic map and fractional chaosMultimedia Tools and Applications10.1007/s11042-020-10373-y80:8(12155-12173)Online publication date: 1-Mar-2021
  • (2018)Are Timing-Based Side-Channel Attacks Feasible in Shared, Modern Computing Hardware?International Journal of Organizational and Collective Intelligence10.4018/IJOCI.20180401038:2(32-59)Online publication date: 1-Apr-2018
  • (2018)ret2specProceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security10.1145/3243734.3243761(2109-2122)Online publication date: 15-Oct-2018
  • (2018)On the bifurcation of Marottos map and its application in image encryptionJournal of Computational and Applied Mathematics10.1016/j.cam.2017.07.010328:C(177-196)Online publication date: 15-Jan-2018
  • (2018)A new simple one-dimensional chaotic map and its application for image encryptionMultimedia Tools and Applications10.1007/s11042-017-5594-977:16(21445-21462)Online publication date: 1-Aug-2018
  • (2017)A Survey of Timing Channels and CountermeasuresACM Computing Surveys10.1145/302387250:1(1-39)Online publication date: 10-Mar-2017
  • (2017)An image encryption algorithm based on Baker map with varying parameterMultimedia Tools and Applications10.1007/s11042-016-3925-x76:15(16511-16527)Online publication date: 1-Aug-2017
  • (2015)Cache template attacksProceedings of the 24th USENIX Conference on Security Symposium10.5555/2831143.2831200(897-912)Online publication date: 12-Aug-2015
  • (2014)FLUSH+RELOADProceedings of the 23rd USENIX conference on Security Symposium10.5555/2671225.2671271(719-732)Online publication date: 20-Aug-2014
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