Fault Detection of Moore Finite State Machines by Structural Models
Pages 394 - 409
Abstract
The fault detection is an important task in the design of fault-tolerant finite state machines (FSMs). The paper describes structural models of Moore FSM for detecting multiple faults in various elements of the FSM and preventing their negative impact on the controlled object. The considered structural models allow detecting invalid transitions between FSM states, invalid input and output vectors, both in each state and for the whole FSM, invalid codes of the present FSM state and the next FSM state. Estimates of the area and performance of the proposed structural models are presented. Experimental results showed that the area overhead for the proposed structural models is from 3 to 26%, which is significantly less than that of the known approaches.
References
[1]
Park S, Kim HT, Lee S, Joo H, and Kim H Survey on anti-drone systems: components, designs, and challenges IEEE Access 2021 9 42635-42659
[2]
Solov’ev, V.V.: ASMD‒FSMD technique in designing signal processing devices on field programmable gate arrays. J. Commun. Technol. Electron. 66(12), 1336–1345 (2021)
[3]
Salauyou, V., Zabrocki, Ł.: Coding techniques in verilog for finite state machine designs in FPGA. In: Saeed, K., Chaki, R., Janev, V. (eds.) CISIM 2019. LNCS, vol. 11703, pp. 493–505. Springer, Cham (2019).
[4]
Lyons RE and Vanderkulk W The use of triple-modular redundancy to improve computer reliability IBM J. Res. Dev. 1962 6 2 200-209
[5]
Aviziens, A.: Fault-tolerant systems. IEEE Trans. Comput. 100(12), 1304–1312 (1976)
[6]
Rochet, R., Leveugle, R., Saucier, G.: Analysis and comparison of fault tolerant FSM architecture based on SEC codes. In: Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, Italy, pp. 9–16. IEEE (1993)
[7]
Niranjan S and Frenzel JF A comparison of fault-tolerant state machine architectures for space-borne electronics IEEE Trans. Reliab. 1996 45 1 109-113
[8]
Carmichael, C.: Triple module redundancy design techniques for Virtex FPGAs. Xilinx Application Note XAPP197, 1 (2001)
[9]
Pontarelli, S., Cardarilli, G.C., Malvoni, A., Ottavi, M., Re, M., Salsano, A.: System-on-chip oriented fault-tolerant sequential systems implementation methodology. In: Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, USA, pp. 455–460. IEEE (2001)
[10]
Lima, F., Carro, L., Reis, R.: Designing fault tolerant systems into SRAM-based FPGAs. In: Proceedings of the 40th Annual Design Automation Conference, Anaheim, USA, pp. 650–655. Machinery (2003)
[11]
Burke, G.R., Taft, S.: Fault tolerant state machines. – nasa.gov (2004)
[12]
Berg, M.: A simplified approach to fault tolerant state machine design for single event upsets. In: Mentor Graphics Users’ Group User2User Conference (2004)
[13]
Tiwari A and Tomko KA Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction IEEE Trans. Reliab. 2005 54 3 459-467
[14]
Cassel, M., Lima, F.: Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), Lake Como, Italia, 6p. IEEE (2006)
[15]
Frigerio, L., Salice, F.: RAM-based fault tolerant state machines for FPGAs. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), Rome, Italy, pp. 312–320. IEEE (2007)
[16]
Azambuja, J.R., Sousa, F., Rosa, L., Kastensmidt, F.L.: Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs. In: 2009 15th IEEE International On-Line Testing Symposium, Lisbon, Portugal, pp. 101–106. IEEE (2009)
[17]
El-Maleh AH and Al-Qahtani AS A finite state machine based fault tolerance technique for sequential circuits Microelectron. Reliab. 2014 54 3 654-661
[18]
Sooraj, S., Manasy, M., Bhakthavatchalu, R.: Fault tolerant FSM on FPGA using SEC-DED code algorithm. In: 2017 International Conference on Technological Advancements in Power and Energy (TAP Energy), Kollam, India, pp. 1–6. IEEE (2017)
[19]
Nidhin, T.S., Bhattacharyya, A., Behera, R.P., Jayanthi, T., Velusamy, K.: Verification of fault tolerant techniques in finite state machines using simulation based fault injection targeted at FPGAs for SEU mitigation. In: 2017 4th International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India, pp. 153–157. IEEE (2017)
[20]
Choi, S., Park, J., Yoo, H.: Area-efficient fault tolerant design for finite state machines. In: 2020 International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, pp. 1–2. IEEE (2020)
[21]
Verducci, O., Oliveira, D.L., Batista, G.: Fault-tolerant finite state machine quasi delay insensitive in commercial FPGA devices. In: 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), Santiago, Chile, pp. 1–4. IEEE (2022)
[22]
Klimowicz, A. S., Solov’ev, V.V.: Structural models of finite-state machines for their implementation on programmable logic devices and systems on chip. J. Comput. Syst. Sci. Int. 54(2), 230–242 (2015)
[23]
Solov’ev V.V.: Synthesis of fast finite state machines on programmable logic integrated circuits by splitting internal states. J. Comput. Syst. Sci. Int. 61(3), 358–369 (2022)
[24]
Yang, S.: Logic synthesis and optimization benchmarks user guide: version 3.0. Research Triangle Park, NC, USA: Microelectronics Center of North Carolina (MCNC), pp. 502–508 (1991)
[25]
Klimovich, A.S., Solov’ev V.V.: Transformation of a mealy finite-state machine into a Moore finite-state machine by splitting internal states. J. Comput. Syst. Sci. Int. 49(6) 900–908 (2010)
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Published In
Sep 2023
520 pages
ISBN:978-3-031-42822-7
DOI:10.1007/978-3-031-42823-4
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 22 September 2023
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