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Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology

Authors:

Xu Yang,

Chris WuAuthors Info & Claims

Journal of Computer Science and Technology, Volume 22, Issue 1

Pages 1 - 14

https://doi.org/10.1007/s11390-007-9000-3

Published: 01 January 2007 Publication History

Abstract

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

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Cited By

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Wang HGao XChen YTang DHu WCheung PWawrzynek J(2010)A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723160(283-283)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723160
Wang DHu YLi HLi X(2008)Design-for-testability features and test implementation of a giga hertz general purpose microprocessorJournal of Computer Science and Technology10.1007/s11390-008-9193-023:6(1037-1046)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1007/s11390-008-9193-0
Hu WWang J(2008)Making effective decisions in computer architects' real-worldJournal of Computer Science and Technology10.1007/s11390-008-9158-323:4(620-632)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11390-008-9158-3

Index Terms

Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology

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cover image Journal of Computer Science and Technology

Journal of Computer Science and Technology Volume 22, Issue 1

January 2007

167 pages

ISSN:1000-9000

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 January 2007

Revised: 05 December 2006

Received: 27 September 2006

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Wang HGao XChen YTang DHu WCheung PWawrzynek J(2010)A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723160(283-283)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723160
Wang DHu YLi HLi X(2008)Design-for-testability features and test implementation of a giga hertz general purpose microprocessorJournal of Computer Science and Technology10.1007/s11390-008-9193-023:6(1037-1046)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1007/s11390-008-9193-0
Hu WWang J(2008)Making effective decisions in computer architects' real-worldJournal of Computer Science and Technology10.1007/s11390-008-9158-323:4(620-632)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11390-008-9158-3

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Microarchitecture of the Godson-2 processor

Out-of-order vector architectures

Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor

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